4 PERIPHERAL CIRCUITS
Register name | Address | Bit | Name | Function |
|
|
|
| Setting | Init. | R/W | Remarks | |||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |||
Serial I/F Ch.0 | 00401E0 | D7 | TXD07 | Serial I/F Ch.0 transmit data |
|
|
| 0x0 to 0xFF(0x7F) | X | R/W | |||||||
transmit data | (B) | D6 | TXD06 | TXD07(06) = MSB |
|
|
|
|
|
|
|
|
|
| X |
| mode does not use |
register |
| D5 | TXD05 | TXD00 = LSB |
|
|
|
|
|
|
|
|
|
| X |
| TXD07. |
|
| D4 | TXD04 |
|
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D3 | TXD03 |
|
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D2 | TXD02 |
|
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D1 | TXD01 |
|
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D0 | TXD00 |
|
|
|
|
|
|
|
|
|
|
| X |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |||
Serial I/F Ch.0 | 00401E1 | D7 | RXD07 | Serial I/F Ch.0 receive data |
|
|
| 0x0 to 0xFF(0x7F) | X | R | |||||||
receive data | (B) | D6 | RXD06 | RXD07(06) = MSB |
|
|
|
|
|
|
|
|
|
| X |
| mode does not use |
register |
| D5 | RXD05 | RXD00 = LSB |
|
|
|
|
|
|
|
|
|
| X |
| RXD07 (fixed at 0). |
|
| D4 | RXD04 |
|
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D3 | RXD03 |
|
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D2 | RXD02 |
|
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D1 | RXD01 |
|
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D0 | RXD00 |
|
|
|
|
|
|
|
|
|
|
| X |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Serial I/F Ch.0 | 00401E2 | – | – |
|
|
|
|
|
| – |
|
| – | – | 0 when being read. | ||
status register | (B) | D5 | TEND0 | Ch.0 | 1 |
| Transmitting |
| 0 |
| End | 0 | R |
| |||
|
| D4 | FER0 | Ch.0 flaming error flag | 1 |
| Error |
|
|
| 0 |
| Normal | 0 | R/W | Reset by writing 0. | |
|
| D3 | PER0 | Ch.0 parity error flag | 1 |
| Error |
|
|
| 0 |
| Normal | 0 | R/W | Reset by writing 0. | |
|
| D2 | OER0 | Ch.0 overrun error flag | 1 |
| Error |
|
|
| 0 |
| Normal | 0 | R/W | Reset by writing 0. | |
|
| D1 | TDBE0 | Ch.0 transmit data buffer empty | 1 |
| Empty |
|
| 0 |
| Buffer full | 1 | R |
| ||
|
| D0 | RDBF0 | Ch.0 receive data buffer full | 1 |
| Buffer full |
|
| 0 |
| Empty | 0 | R |
| ||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Serial I/F Ch.0 | 00401E3 | D7 | TXEN0 | Ch.0 transmit enable | 1 |
| Enabled |
|
| 0 |
| Disabled | 0 | R/W |
| ||
control register | (B) | D6 | RXEN0 | Ch.0 receive enable | 1 |
| Enabled |
|
| 0 |
| Disabled | 0 | R/W |
| ||
|
| D5 | EPR0 | Ch.0 parity enable | 1 |
| With parity |
| 0 |
| No parity | X | R/W | Valid only in | |||
|
| D4 | PMD0 | Ch.0 parity mode selection | 1 |
| Odd |
|
|
| 0 |
| Even | X | R/W | asynchronous mode. | |
|
| D3 | STPB0 | Ch.0 stop bit selection | 1 |
| 2 bits |
|
|
| 0 |
| 1 bit | X | R/W |
| |
|
| D2 | SSCK0 | Ch.0 input clock selection | 1 |
| #SCLK0 |
|
| 0 |
| Internal clock | X | R/W |
| ||
|
| D1 | SMD01 | Ch.0 transfer mode selection | SMD0[1:0] |
| Transfer mode | X | R/W |
| |||||||
|
| D0 | SMD00 |
|
| 1 |
| 1 | X |
|
| ||||||
|
|
|
|
|
| 1 |
| 0 |
|
|
| ||||||
|
|
|
|
|
| 0 |
| 1 | Clock sync. Slave |
|
|
| |||||
|
|
|
|
|
| 0 |
| 0 | Clock sync. Master |
|
|
| |||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Serial I/F Ch.0 | 00401E4 | – | – |
|
|
|
|
|
| – |
|
| – | – | 0 when being read. | ||
IrDA register | (B) | D4 | DIVMD0 | Ch.0 async. clock division ratio | 1 |
| 1/8 |
|
|
| 0 |
| 1/16 | X | R/W |
| |
|
| D3 | IRTL0 | Ch.0 IrDA I/F output logic inversion | 1 |
| Inverted |
|
| 0 |
| Direct | X | R/W | Valid only in | ||
|
| D2 | IRRL0 | Ch.0 IrDA I/F input logic inversion | 1 |
| Inverted |
|
| 0 |
| Direct | X | R/W | asynchronous mode. | ||
|
| D1 | IRMD01 | Ch.0 interface mode selection | IRMD0[1:0] |
|
|
| I/F mode | X | R/W |
| |||||
|
| D0 | IRMD00 |
|
| 1 |
| 1 |
|
|
| reserved | X |
|
| ||
|
|
|
|
|
| 1 |
| 0 |
|
|
| IrDA 1.0 |
|
|
| ||
|
|
|
|
|
| 0 |
| 1 |
|
|
| reserved |
|
|
| ||
|
|
|
|
|
| 0 |
| 0 |
|
| General I/F |
|
|
| |||
S1C33L03 PRODUCT PART | EPSON |