V DMA BLOCK: HSDMA
Register name | Address | Bit | Name | Function |
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| Setting | Init. | R/W | Remarks | ||||
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0048254 | DF | S3ADRL15 | D) Ch.3 source address[15:0] |
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| X | R/W |
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DMA Ch.3 | (HW) | DE | S3ADRL14 | S) Ch.3 memory address[15:0] |
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| X |
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| DD | S3ADRL13 |
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| X |
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source address |
| DC | S3ADRL12 |
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| X |
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| DB | S3ADRL11 |
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| X |
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| DA | S3ADRL10 |
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| X |
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Note: |
| D9 | S3ADRL9 |
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| X |
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D) Dual address |
| D8 | S3ADRL8 |
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| X |
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mode |
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| D7 | S3ADRL7 |
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| X |
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S) Single |
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| D6 | S3ADRL6 |
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| X |
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address |
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| D5 | S3ADRL5 |
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| X |
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mode |
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| D4 | S3ADRL4 |
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| X |
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| D3 | S3ADRL3 |
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| X |
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| D2 | S3ADRL2 |
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| X |
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| D1 | S3ADRL1 |
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| X |
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| D0 | S3ADRL0 |
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| X |
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0048256 | DF | – | reserved |
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| – |
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| – | – |
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DMA Ch.3 | (HW) | DE | DATSIZE3 | Ch.3 transfer data size | 1 | Half word |
| 0 | Byte | 0 | R/W |
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| DD | S3IN1 | D) Ch.3 source address control | S3IN[1:0] |
| Inc/dec | 0 | R/W |
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source address |
| DC | S3IN0 | S) Ch.3 memory address control | 1 | 1 |
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| Inc.(no init) | 0 |
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| 1 | 0 |
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| Inc.(init) |
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| 0 | 1 |
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| Dec.(no init) |
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Note: |
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| 0 | 0 |
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| Fixed |
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D) Dual address |
| DB | S3ADRH11 | D) Ch.3 source address[27:16] |
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| X | R/W |
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mode |
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| DA | S3ADRH10 | S) Ch.3 memory address[27:16] |
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| X |
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S) Single |
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| D9 | S3ADRH9 |
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| X |
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address |
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| D8 | S3ADRH8 |
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| X |
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mode |
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| D7 | S3ADRH7 |
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| X |
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| D6 | S3ADRH6 |
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| X |
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| D5 | S3ADRH5 |
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| X |
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| D4 | S3ADRH4 |
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| X |
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| D3 | S3ADRH3 |
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| X |
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| D2 | S3ADRH2 |
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| X |
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| D1 | S3ADRH1 |
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| X |
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| D0 | S3ADRH0 |
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| X |
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0048258 | DF | D3ADRL15 | D) Ch.3 destination address[15:0] |
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| X | R/W |
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DMA Ch.3 | (HW) | DE | D3ADRL14 | S) Invalid |
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| X |
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| DD | D3ADRL13 |
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| X |
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destination |
| DC | D3ADRL12 |
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| X |
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address |
| DB | D3ADRL11 |
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| X |
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register |
| DA | D3ADRL10 |
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| X |
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| D9 | D3ADRL9 |
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| X |
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Note: |
| D8 | D3ADRL8 |
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| X |
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D) Dual address |
| D7 | D3ADRL7 |
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| X |
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mode |
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| D6 | D3ADRL6 |
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| X |
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S) Single |
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| D5 | D3ADRL5 |
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| X |
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address |
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| D4 | D3ADRL4 |
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| X |
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mode |
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| D3 | D3ADRL3 |
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| X |
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| D2 | D3ADRL2 |
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| X |
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| D1 | D3ADRL1 |
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| X |
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| D0 | D3ADRL0 |
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| X |
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EPSON | S1C33L03 FUNCTION PART |