
APPENDIX: I/O MAP
Register name | Address | Bit | Name | Function |
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| Setting | Init. | R/W | Remarks | |||
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004014A | – | reserved |
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|
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| – |
| – | – | 0 when being read. | |||
clock control | (B) | D3 | P16TON3 | 1 | On |
|
| 0 | Off | 0 | R/W |
| ||
register |
| D2 | P16TS32 | P16TS3[2:0] |
| Division ratio | 0 | R/W | θ: selected by | |||||
|
| D1 | P16TS31 | clock division ratio selection | 1 |
| 1 | 1 |
|
| θ/4096 | 0 |
| Prescaler clock select |
|
| D0 | P16TS30 |
| 1 |
| 1 | 0 |
|
| θ/1024 | 0 |
| register (0x40181) |
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|
|
| 1 |
| 0 | 1 |
|
| θ/256 |
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| 1 |
| 0 | 0 |
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| θ/64 |
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|
| 0 |
| 1 | 1 |
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| θ/16 |
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| 0 |
| 1 | 0 |
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| θ/4 |
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| 0 |
| 0 | 1 |
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| θ/2 |
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| 0 |
| 0 | 0 |
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| θ/1 |
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| |
004014B | – | reserved |
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|
|
| – |
| – | – | 0 when being read. | |||
clock control | (B) | D3 | P16TON4 | 1 | On |
|
| 0 | Off | 0 | R/W |
| ||
register |
| D2 | P16TS42 | P16TS4[2:0] |
| Division ratio | 0 | R/W | θ: selected by | |||||
|
| D1 | P16TS41 | clock division ratio selection | 1 |
| 1 | 1 |
|
| θ/4096 | 0 |
| Prescaler clock select |
|
| D0 | P16TS40 |
| 1 |
| 1 | 0 |
|
| θ/1024 | 0 |
| register (0x40181) |
|
|
|
|
| 1 |
| 0 | 1 |
|
| θ/256 |
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|
| 1 |
| 0 | 0 |
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| θ/64 |
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| 0 |
| 1 | 1 |
|
| θ/16 |
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| 0 |
| 1 | 0 |
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| θ/4 |
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| 0 |
| 0 | 1 |
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| θ/2 |
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| 0 |
| 0 | 0 |
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| θ/1 |
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| |
004014C | – | reserved |
|
|
|
| – |
| – | – | 0 when being read. | |||
clock control | (B) | D3 | P16TON5 | 1 | On |
|
| 0 | Off | 0 | R/W |
| ||
register |
| D2 | P16TS52 | P16TS5[2:0] |
| Division ratio | 0 | R/W | θ: selected by | |||||
|
| D1 | P16TS51 | clock division ratio selection | 1 |
| 1 | 1 |
|
| θ/4096 | 0 |
| Prescaler clock select |
|
| D0 | P16TS50 |
| 1 |
| 1 | 0 |
|
| θ/1024 | 0 |
| register (0x40181) |
|
|
|
|
| 1 |
| 0 | 1 |
|
| θ/256 |
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|
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| 1 |
| 0 | 0 |
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| θ/64 |
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| 0 |
| 1 | 1 |
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| θ/16 |
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| 0 |
| 1 | 0 |
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| θ/4 |
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| 0 |
| 0 | 1 |
|
| θ/2 |
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| 0 |
| 0 | 0 |
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| θ/1 |
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| ||
004014D | D7 | P8TON1 | 1 | On |
|
| 0 | Off | 0 | R/W |
| |||
clock control | (B) | D6 | P8TS12 | P8TS1[2:0] |
| Division ratio | 0 | R/W | θ: selected by | |||||
register |
| D5 | P8TS11 | clock division ratio selection | 1 |
| 1 | 1 |
|
| θ/4096 | 0 |
| Prescaler clock select |
|
| D4 | P8TS10 |
| 1 |
| 1 | 0 |
|
| θ/2048 | 0 |
| register (0x40181) |
|
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|
|
| 1 |
| 0 | 1 |
|
| θ/1024 |
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|
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| 1 |
| 0 | 0 |
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| θ/512 |
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| |
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| 0 |
| 1 | 1 |
|
| θ/256 |
|
| generate the OSC3 |
|
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|
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| 0 |
| 1 | 0 |
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| θ/128 |
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| |
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| 0 |
| 0 | 1 |
|
| θ/64 |
|
| waiting period. |
|
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|
|
| 0 |
| 0 | 0 |
|
| θ/32 |
|
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|
|
| D3 | P8TON0 | 1 | On |
|
| 0 | Off | 0 | R/W |
| ||
|
| D2 | P8TS02 | P8TS0[2:0] |
| Division ratio | 0 | R/W | θ: selected by | |||||
|
| D1 | P8TS01 | clock division ratio selection | 1 |
| 1 | 1 |
|
| θ/256 | 0 |
| Prescaler clock select |
|
| D0 | P8TS00 |
| 1 |
| 1 | 0 |
|
| θ/128 | 0 |
| register (0x40181) |
|
|
|
|
| 1 |
| 0 | 1 |
|
| θ/64 |
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| 1 |
| 0 | 0 |
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| θ/32 |
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| |
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|
| 0 |
| 1 | 1 |
|
| θ/16 |
|
| generate the DRAM |
|
|
|
|
| 0 |
| 1 | 0 |
|
| θ/8 |
|
| refresh clock. |
|
|
|
|
| 0 |
| 0 | 1 |
|
| θ/4 |
|
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| 0 |
| 0 | 0 |
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| θ/2 |
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EPSON | S1C33L03 FUNCTION PART |