3. Instruction

Set

API

Mnemonic

 

Operands

Function

 

 

Controllers

 

108

 

CRC

P

 

 

 

CRC checksum

 

 

 

ES2/EX2 SS2 SA2 SX2

 

 

 

 

 

 

 

SE

 

 

Type

Bit Devices

 

 

Word devices

 

 

 

Program Steps

 

OP

 

X

Y

M

S

K

H KnX KnY KnM KnS T C

D

E

F

CRC, CRCP: 7 steps

 

 

S

 

 

 

 

 

 

 

*

 

 

 

 

 

n

 

 

 

 

*

*

 

*

 

 

 

 

D

 

 

 

 

 

 

 

*

 

 

 

 

 

 

 

 

 

 

 

 

PULSE

 

16-bit

 

32-bit

 

 

ES2/EX2

SS2

SA2

SX2

ES2/EX2

SS2

SA2

SX2

ES2/EX2

SS2

SA2

SX2

 

 

SE

SE

SE

Operands:

 

 

 

 

 

 

 

 

 

 

 

S: Starting device for RTU mode checksum n: Data length for CRC operation (n = K1~K256)

D:

Starting device for storing the operation result

 

 

 

 

 

 

 

 

 

 

 

Explanations:

1.n: n must be an even number. If n is out of range, an error will occur and the instruction will not be executed. At this time, M1067 and M1068 = ON and error code H’0E1A will be recorded in D1067.

2.16-bit mode: When CRC instruction operates with M1161 = OFF, hexadecimal data starting from S is divided into high byte and low byte and the checksum operation is operated on n number of bytes. After this, operation result will be stored in both hi-byte and low byte of D.

3.8-bit mode: When CRC instruction operates with M1161 = ON, hexadecimal data starting from S is divided into high byte (invalid) and low byte and the checksum operation is operated on n number of low bytes. After this, operation result will be stored in low bytes of D (Consecutive 2 registers).

4.Flag: M1161 8/16-bit mode

3 - 2 9 3

Page 409
Image 409
Delta DVP-ES2/EX2/SS2/SA2/SX2/SE manual KnX KnY KnM KnS T C CRC, Crcp 7 steps