Epson S1C33L03 manual 623

APPENDIX: I/O MAP

A-1

Register name	Address	Bit	Name	Function				Setting					Init.	R/W	Remarks
SDRAM area	039FFC0	D7	SDRAR0	Area 7/13 configuration	1	SDRAM				0		Not SDRAM	0	R/W
configuration	(B)	D6	SDRAR1	Area 8/14 configuration	1	SDRAM				0		Not SDRAM	0	R/W
register		D5–4	–	reserved					–				–	–	0 when being read.
		D3	SDRPC0	#CE7/13 pin configuration	1	#SDCE0				0		#CE7/13	0	R/W
		D2	SDRPC1	#CE8/14 pin configuration	1	#SDCE1				0		#CE8/14	0	R/W
		D1–0	–	reserved					–				–	–	0 when being read.
SDRAM	039FFC1	D7	SDRENA	Enable SDRAM signals	1	Enabled				0		Disabled	0	R/W
control register	(B)	D6	SDRINI	Start SDRAM power up	1	Start				0		–	0	R/W	0 when being read.
		D5	SDRSRF	Enable SDRAM self-refresh	1	Enabled				0		Disabled	0	R/W
		D4	SDRIS	Initial command sequence	1	1 precharge				0		1 precharge	0	R/W
						2 set reg.						2 refresh
						3 refresh						3 set reg.
		D3	SDRCLK	Keep SDCLK during self-refresh	1	Kept				0		Stopped	1	R/W
		D2–0	–	reserved					–				–	–	0 when being read.
SDRAM	039FFC2	D7	–	reserved					–				–	–	0 when being read.
address	(B)	D6–5	SDRCA1	SDRAM page size	SDRCA[1:0]					Page size			0	R/W
configuration			SDRCA0	(column range)	1			1			reserved		0
register					1			0	1K (SDA[9:0])
					0			1	512 (SDA[8:0])
					0			0	256 (SDA[7:0])
		D4	–	reserved					–				–	–	0 when being read.
		D3–2	SDRRA1	SDRAM row addressing range	SDRRA[1:0]				Addressing range				0	R/W
			SDRRA0		1			1			reserved		0
					1			0	8K (SDA[12:0])
					0			1	4K (SDA[11:0])
					0			0	2K (SDA[10:0])
		D1	SDRBA	Number of SDRAM banks	1	4 banks				0		2 banks	0	R/W
		D0	–	reserved					–				–	–	0 when being read.
SDRAM	039FFC3	D7	–	reserved					–				–	–	0 when being read.
mode set-up	(B)	D6–5	SDRCL1	SDRAM CAS latency	SDRCL[1:0]					CAS latency			1	R/W
register			SDRCL0		1			0	2 CAS latency				1
		D4	–	reserved					–				–	–	0 when being read.
		D3–2	SDRBL1	SDRAM burst length	SDRBL[1:0]					Burst length			1	R/W
			SDRBL0		1			1			8		1
					1			0			4
					0			1			2
					0			0			1
		D1–0	–	reserved					–				–	–	0 when being read.
SDRAM	039FFC4	D7–5	SDRTRAS2	SDRAM tRAS spec	SDRTRAS[2:0]				Number of clocks				0	R/W
timing set-up	(B)		SDRTRAS1		1		1	1			7		0
register 1			SDRTRAS0		1		1	0			6		0
					1		0	1			5
					1		0	0			4
					0		1	1			3
					0		1	0			2
					0		0	1			1
					0		0	0			8
		D4–3	SDRTRP1	SDRAM tRP spec	SDRTRP[1:0]				Number of clocks				0	R/W
			SDRTRP0		1			1			3		0
					1			0			2
					0			1			1
					0			0			4
		D2–0	SDRTRC2	SDRAM tRC spec	SDRTRC[2:0]				Number of clocks				0	R/W
			SDRTRC1		1		1	1			7		0
			SDRTRC0		1		1	0			6		0
					1		0	1			5
					1		0	0			4
					0		1	1			3
					0		1	0			2
					0		0	1			1
					0		0	0			8

B-ap

S1C33L03 FUNCTION PART EPSON B-APPENDIX-43