Fujitsu manual M2488 Product Guide Design Architecture Scsi BUS, Microprocessor Control

M2488 PRODUCT GUIDE DESIGN ARCHITECTURE

SCSI BUS

DATA BUFFER	FORMATTER
WITH EDRC
FORMATTING

								WRITE
			4- 256K x 18				WFMT	HEAD
								LOGIC
	SCSI
SCSI
DRIVERS	PROTOCOL
RECEIVERS	CONTROLLER		DRAM			9
							AXP	RS
	MB86603		SDDP
		18				9
SN75LBC976						BUS
							DSKW	READ
		FIFO SRAM	SG			CP		HEAD
								LOGIC
			(SGC)	COMPRESSION
		SRAM					RCTL
		32K x 16	CE
			SG	EDRC			RSVPI/F
		CPBUS	(SGD)		CPBUS
MICROPROCESSOR						COMPANION
CP						PROCESSOR
			DE			CHIP
						(RSVP Controller)		PROCESSORSERVO RAMSHARED INTERFACE
MB86930		(1 Mbyte CS)	MASK-
SPARC lite			FLASH			PCC
		DRAM	NVRAM
			MB8486A
		2 - 256K x 18	8k x 8
			ROM
						DRV/RCV		RS232
			2 x 512K x 8

Figure 2-2. DTC PCA Block Diagram

packet, to be built without requiring additional buffering. Data buffering increases overall perfor- mance by allowing data streaming since the buffer can mask or eliminate some tape repositions.

The EDRC chip set consists of a compression engine (CE), a decompression engine (DE), and a data control function (SG). The SG LSI is used twice in the design, once each for the CE and DE. The complete chip set is designed to operate at the full data path rate of 20 MB/s. In addition, The com- pression SG input FIFO is 64k bytes for compression data caching. If compression retries are ever required, retries can automatically be performed without host intervention.

2-3.4 Microprocessor Control

A 20MHz MB68930 Sparc-lite MPU is the single Control Processor (CP) used for the controller requirements. The controller CP communicates directly to the drive servo CP via dual-port RAM. The RSVP (Read Signal Verification Processor) is a 10 Mhz, 24-bit, fixed instruction sequencer that is embedded inside the PCC (Processor Companion Chip). It requires less than 4200 basic cells of the 22,800 cells in the PCC. The RSVP provides the dedicated formatter signal processing needed to support the CP with the time critical formatter control. It allows the controller firmware architecture to use event driven multi-tasking for the CP code and allow the RSVP to handle dedicated read signal polling. The RSVP presents interrupts to the CP based on drive read interface signals which are pre- processed; polled, monitored, filtered, and conditioned as required.

April 1997 CG00000-011503 REV. A 2-3