CACHE SUBSYSTEMS

Each direct mapped Cilche address has two parts. The first part, called the cache index field, contains enough bits to specify a block location within the cache. The second part, called the tag field, contains enough bits to distinguish a block from other blocks that

.may be stored at a particular cache location.

For example, consider a 64-kilobyte direcf mapped cache that contains 16K 32-bit loca- tions and caches 16 megabytes of main memory. The cache index field must include 14 bits to select one of the 16K blocks in the cache, plus 2 bits (or 4 byte Enables) to select a byte from the 4-byte block. The tag field must be 8 bits wide to identify One of the 256 blocks that can occupy the seleCted cache location. The remaining 8 bits of the 32-bit Intel386 DX microprocessor address are decoded to select the cache subsystem from among other memories in the memory space. The direct-mapped cache organiza- tion is shown in Figure 7-3.

32.BIT

131

 

24123

. 16

15

 

 

o

 

PROCESSOR

ICACHE/DRAM I

 

 

INDEX

 

 

ADDRESS

SE~ECT

TAG

 

 

 

 

 

 

 

 

 

 

j.-64K CACHE = 16 BITS--+!

 

 

 

 

1+--16 MEGABYTE DRAM = 24 BITS----+!

 

 

 

 

 

 

 

 

DATA

INDEX

TAG

 

 

 

 

 

 

 

 

FFFC

 

 

 

 

 

 

 

 

11223344

FFF8

 

INDEX

TAG

 

DATA

 

 

 

 

0010

FF

 

 

 

 

 

0000

 

 

 

 

 

I

FFFC

01

 

12345678

 

 

 

 

0008

 

f...J

 

 

 

0004

FFF8

FF

 

11223344

 

 

 

 

 

 

--

0000

0010

 

 

 

 

 

 

 

OOOC

 

 

87654321

P

 

 

-

 

I

0008

00

 

'---

12345678

FFFC

0004

01

 

11235813

 

 

FFF8

0000

00

 

13579246

I-

-

 

 

 

 

 

 

 

 

 

(14 BITS) j.8 BIT~

j+32BITS~

 

 

 

0010

01

 

 

 

OOOC

 

 

 

 

 

 

 

 

0008

I~

 

64KSRAM CACHE

 

 

 

11235813

0004

 

 

 

 

 

 

 

 

0000

 

 

 

 

 

 

 

 

FFFC

 

 

 

 

 

 

 

 

FFF8

 

 

 

 

 

 

 

 

.0010

 

 

 

 

 

 

 

 

OOOC

 

 

 

 

 

 

 

87654321

0008

 

 

 

 

 

 

 

 

0004

 

 

 

 

 

 

 

13579246

0000

j+32BITS.j

16 MEGABYTE DRAM

231732;7·3

Figure 7-3. Direct Mapped Cache Organization

7-5

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Image 129
Intel 386 manual Direct Mapped Cache Organization