CHAPTER 6
MEMORY INTERFACING
The Intel386 DX microprocessor high-speed bus interface has many features that con- tribute to high-performance memory interfaces. This chapter outlines approaches to designing memory systems that utilize these features, describes memory design consider- ations, and lists a number of useful examples. The concepts illustrated by these examples apply to a wide variety of memory system implementations.
6.1 MEMORY SPEED VERSUS PERFORMANCE AND COST
In a high-performance microprocessing system, overall system performance is linked to the performance of memory subsystems. Most bus cycles in a typical microprocessing system are used to access memory because memory is used to store programs as well as the data used in processing.
To realize the performance potential of the Inte1386 DX microprocessor, a system must use relatively fast memory. A high-performance processor coupled with low-performance memory provides no better throughput than a less expensive low-performance processor. Fast memory devices, however, cost more than slow memory devices.
The cost-performance tradeoff can be mediated by partitioning functions and using a combination of both fast and slow memories. If the most frequently used functions are placed in fast memory and all other functions are placed in slow memory, high perfor- mance for most operations can be achieved at a cost significantly less than that of a fast memory subsystem. For example, in a RAM-based system that uses read-only memory devices primarily during initialization, the PROM or EPROM can be slow (requiring three to four wait states) and yet have little effect on system performance. RAM memory can also be partitioned into fast local memory and slower system memory. Other perfor- mance considerations are described in detail in Chapter 4.
The relationship between memory subsystem performance and the speed of individual memory devices is determined by the design of the memory subsystem. Cache systems, which couple a small cache memory with a larger main memory, are described in Chap- ter 7. Basic memory interfaces are described in this chapter.
6.2 BASIC MEMORY INTERFACE
The high performance and flexibility of the Intel386 DX microprocessor local bus inter- face plus the availability of programmable and semi-custom logic (programmable logic arrays, for example) make it practical to design custom bus control logic that meets the requirements of a particular system. Standard logic components can generate the bus control signals needed to interface the Intel386 DX microprocessor with memory and I/O devices. The basic memory interface is discussed in this chapter; the basic I/O inter- face is presented in Chapter 8.
