Intel 386 manual BUS Timing

lOCAL BUS INTERFACE

3.2 BUS TIMING

This section describes timing requirements for read cycles, write cycles, and the READY# signal.

All Inte1386 DX microprocessor signals have setup and hold time requirements relative to CLK2. The timings of certain signals relative to one another depends on whether address pipelining is used. These facts must be considered when determining external logic needed to facilitate bus cycles.

The analyses that follow are based on the assumption that a 20-MHz Intel386 DX micro- processor is used. If the processor is operated at a different frequency, the timings will change accordingly. Example worst-case signal parameter values from the 386'" DX Microprocessor Data Sheet (Order Number 231630) are used; consult the most recent data sheet to confirm these values. Also note that delay times and setup times must be factored into the timing of system response and interaction with the Inte1386 DX micro- processor to ensure comfortable margins for all critical timings.

3.2.1 Read Cycle Timing

For read cycles, the minimum amount of time from the output of valid addresses to the reading of the data bus sets an upper limit on memory access times (including address decoding time). In a non-pipelined address cycle, this time is

Four ClK2 cycles (at 20 MHz)		-	100 nanoseconds
-	A31-A2 output delay (maximum)		30 nanoseconds
-	D31-DO input setup (minimum)	-	11 nanoseconds
			59 nanoseconds

With address pipelining and no wait states, the address is valid one CLK cycle earlier:

Non-pipelined value	59 nanoseconds
+ One ClK cycle (2 CLK2 cycles)	+ 50 nanoseconds
	109 nanoseconds

For both cases above, each wait state in the bus cycle adds 50 nanoseconds.

3.2.2 Write Cycle Timing

For write cycles, the elapsed time from the output of valid address to the end of the cycle determines how quickly the external logic must decode and latch the address. In a non- pipelined address cycle, this time is

Four CLK2 cycles (at 20 MHz)	-	100 nanoseconds
- A31-A2 output delay (maximum)		30	nanoseconds
		70	nanoseconds
(With address pipelining)	(+	50	nanoseconds)
(With N wait states)	(+ N* 50		nanoseconds)
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