Intel 386 manual Figures

TABLE OF CONTENTS

Figures

Figure		Title				Page
1-1	Intel386™	DX Microprocessor System Block Diagram				1-2
, 1-2	Micro Channel-Compatible Solution with 82311			Chip Set		1-3
2-1	Instruction Pipelining				.	2-1
2-2	Intel386™	DX Microprocessor Functional Units		.............................................		2-3
3-1	ClK2 and ClK Relationship				.	3-4
3-2	Intel386™	DX CPU Bus States Timing Example		......................................	:	3-5
3-3	Bus State Diagram (Does Not Include Address Pipelining)					3-6
3-4	Non-Pipelined Address and Pipelined Address Differences					3-7
3-5	Consecutive Bytes in Hardware Implementation			...........................................		3-8
3-6	Address, Data Bus, and Byte Enables for 32-Bit Bus				;	3-9
3-7	Misaligned Transfer			,		3-10
3-8	Non-Pipelined Address Read Cycles				.	3-12
3-9	Non-Pipelined Address Write Cycles				.	3-14
3-10	Pipelined Address Cycles				.	3-15
3-11	Interrupt Acknowledge Bus Cycles				.	3-17
3-12	Internal NA# and BS16# logic				.	3-19
3-13	32-Bit and 16-Bit Bus Cycle Timing				;.	3-20
3-14	32-Bit and 16-Bit Data Addressing				.	3-21
3-15	Using ClK to Determine Bus Cycle Start		.....................................................		.	3-25
3-16	Clock Generator				.	3-26
3-17	'ADS#Synchronizer				.	3-27
3-18	Error Condition Caused by Unlocked Cycles				.	3-31
3-19	lOCK# Signal during Address Pipelining				.	3-32
3-20	Bus State Diagram with HOLD State				.	3-34
3-21	RESET, ClK, and ClK2 Timing				.	3-36
5-1	Intel386™	DX CPU System with Intel387'MDX Math Coprocessor				5-3
5-2 r	Pseudo-Synchronous Interface				.	5-5
5-3	Software Routine to Recognize the Coprocessor				:	5-7
6-1	Basic Memory Interface Block Diagram				,	6-2
6-2	PlD Equation arid Device Implementation				.	6-5
6-3	85C220, EPlD Macrocell Architecture				.	6-6
6-4	I/O Controller Schematic				.	6-8
6-5	250 Nanosecond EPROM Timing Diagram				.	6-10
6-6	3-ClK DRAM Controller Schematic		~		.	6-15
6-7	3-ClK DRAM Controller Cycles				.	6-18
6-8	Timing Waveforms (Read Cycle)				,	6-19
6-9	Timing Waveforms (Write Cycle)				.	6-20
6-10	Avoiding Data Bus Contention				.	6-24
6-11	Tap Delay Line				.	6-27
6-12	Refresh Request Generation				,	6-30
7-1	Cache Memory System				.	7-1
7-2	Fully Associative Cache Organization				:	7-4
7-3	Direct Mapped Cache Organization				,	7-5
7-4	Two-Way Set Associative Cache Organization				.	7-7
7-5	Stale Data Problem				.	7-9
7-6	Bus Watching				.	7-10
7-7	Hardware Transparency				.	7-11
7-8	Non-Cacheable Memory				.	7-12
7-9	Example of Cache Memory Organization		.....................................................		.	7-15
7-10	Intel386™	DX Microprocessor System Bus Structure				7-16
7-11	Intel386™	DX Microprocessor/82385 System Bus Structure				7-17
7-12	Intel386™	DX Microprocessor/82385 Interface			.	7-18
7-13	Direct Mapped Cache without Data Buffers				.	7-20
7-14	Direct Mapped Cache with Data Buffers		.......................................................		.	7-21

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