Intel 386 manual Dram Design Variations

MEMORY INTERFACING

For example consider the minimum RAS# pulse width specification. Instead of:

TRAS = (6 x CLK2) - PLD RegOut Max (RAS# active) + PLD RegOut Min (RAS# inactive)

It would be more realistic to consider

TRAS = (6 x CLK2) - PLD RegOut Skew (RAS# active-inactive)

Where the skew depends on:

The capacitance

- The opposite going signal edges

The skew would even be less for the same signal between two positive or two negative edges. For example TRC, the RAS# cycle time, is measured from RAS# active to RAS# active. The timing analysis would be the number of clock cycles minus the RAS# active-active skew.

6.3.3.9 CAPACITIVE LOADING

The delay of a logic device is affected by the capacitive load on the output. Most devices are specified at a given load and include either a delay versus load graph or a nanosec- onds per picofarad specification. The Intel386 DX microprocessor data sheet includes a delay versus load graph. From this graph a linear approximation of the relay can be made. The data sheet specifies the delay for a particular load. If the actual load is greater than the specified load, an additional delay factor needs to be calculated.

The Intel386 DX microprocessor specifications are made at the 1.5 volt levels. If the component interfaced is specified at another level, it will be necessary to consider the rise times of signals. The Inte1386 DX microprocessor data sheet provides a rise time versus capacitance graph.

6.3.4DRAM Design Variations

6.3.4.13-CLK DESIGN VARIATIONS

Some of the possible variations of the 3-CLK designs are as follows:

•The 3-CLK designs can use any length DRAM in Nxl, Nx4, and Nx8 widths.

•The 3-CLK design can use the internal PLD registers or external TTL registers on the RAS and/or CAS signals.

•Data transceivers are optional. If a data transceiver is used, the DRAM read access must meet the Inte1386 DX microprocessor read-data setup time. If no data trans- ceiver is used, the DRAM read-data-float time must not interfere with the next Intel386 DX microprocessor cycle, particularly if it is a write cycle, and the Inte1386 DX microprocessor data pin loading must not be exceeded.

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