Intel 386 manual Avoiding Data BUS Contention

MEMORY INTERFACING

TDS : Write data setup to CAS#

=(2 x CLK2 period) - Inte1386 DX microprocessor Write Data Valid Delay (T12) - Xcvr Prop Max + PLD RegOut Min (CAS#) + (2 x Or-gate Prop Min)

=50 - 38 - 7 + 1.5 + 6

=12.5 nanoseconds

TDH : Data hold time from CAS# active

=(3 x CLK2 period) - PLD RegOut Max (CAS#) - (2 x Or-gate Prop Max) + (PLD RegOut Min (ALE) + OR-gate Prop Min) + Xcvr Disable Min

=75 - 6 - 12 + (1.5 +3) + 2

=63.5 nanoseconds

6.3.3.6 AVOIDING DATA BUS CONTENTION

Using data transceivers allows write cycles to follow read cycles without additional wait states. Care must be taken to disable the transceivers before changing their direction. Figure 6-10 shows the timing for· a read cycle directly followed by a write cycle.

On the Inte1386 DX microprocessor data bus side of the transceivers the read data stops driving the bus when DEN# goes inactive and the data buffer disables its output.

Txop : Transceiver stops driving the processor side of the data bus

=PLD RegOut Max (ALE#) + Or-gate Prop Max + Xcvr Disable Max

=6 + 6 + 7.5

=19.5 nanoseconds or 5.5 nanoseconds before the start of phase two

The Intel386 DX microprocessor does not start driving write data until a minimum of 4 ns (T12) after the start of phase two so no contention will occur.

On the DRAM side of the transceivers the read cycle ends whenCAS# goes inactive and the DRAMs turn off. The write cycle data will be driven onto the bus at the start of phase one of the next clock after DEN# becomes active.

ToFF : DRAM data turn off from CAS#

=(2 x CLK2 period) - PLD Reg Out Max (CAS#) - (2 x Or-gate Prop Max) + (PLD RegOut Min (ALE) + Or-gate Prop Min) + Xcvr Enable Min

=50 - 6 - 12 + (1.5 + 3) + 3

=39.5 nanoseconds

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