Intel 386 manual 9 8516 Cycle

LOCAL BUS INTERFACE

As with other bus cycles, a halt or shutdown cycle is initiated by activating ADS# and the bus status pins as follows:

•M/IO# and W/R# are driven high, and D/C# is driven low to indicate a halt or shutdown cycle.

•All address bus outputs are driven low. For a halt condition, BE2# is active; for a shutdown condition, BEO# is active. These signals are used by external devices to respond to the halt or shutdown cycle.

READY# must be asserted to complete the halt or shutdown cycle. The Intel386 DX

microprocessor will remain in the halt or shutdown condition until...

•NMI goes high; Intel386 DX microprocessor services the interrupt

•RESET goes high; Inte1386 DX microprocessor is reinitialized

In the halt condition (but not in the shutdown condition), if maskable interrupts are enabled, an active INTR input will cause the Inte1386 DX microprocessor to end the halt cycle to service the interrupt. The Inte1386 DX microprocessor can service processor extension (PEREQ input) requests and HOLD (HOLD input) requests while in the halt or shutdown condition.

3.1.9 8516 Cycle

The Inte1386 DX microprocessor can perform data transfers for both 32-bit and 16-bit data buses. A control input, BSI6#, allows the bus size to be specified for each bus cycle. This dynamic bus sizing gives the Intel386 DX microprocessor flexibility in using 16-bit components and buses.

The BSI6# input causes the Intel386 DX microprocessor to perform data transfers for a 16-bit data bus (using data bus signals DIS-DO) rather than a 32-bit data bus. The Intel3.86 DX microprocessor automatically performs two or three cycles for data trans- fers larger than 16 bits and for misaligned (odd-addressed) 16-bit transfers.

BSI6# must be supplied by external hardware, either through chip select decoding or directly from the addressed device. BSI6# is sampled at the start of Phase 2 only in CLK cycle as long as ADS# is not active. If BSI6# and READY# are sampled low in the same CLK cycle, the Inte1386 DX microprocessor assumes a 16-bit data bus.

The BSI6# control input affects the performance of a data transfer only for data trans- fers in which I} BEO# or BEl# is active and 2) BE2# or BE3#is active at the same time. In these transfers, the Intel386 DX microprocessor must perform two bus cycles using only the lower half of the data bus.

If a BS16 cycle requires. an additional bus cycle, the Intel386 DX microprocessor will retain the current address for the second cycle. Address pipelining cannot be used with BS16 cycles because address pipelining requires that the next address be generated on

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