Intel 386 manual DRAMP2 PLD Equations

DRAM PLD DESCRIPTIONS

module

flag '-r3' 1'~~2' ,'-ul'

title

'80386 Interleaved DRAM Controller pld-2 pipelined 1ws Intel Corporation.'

U34	device	'E~32~';
" Constants:
ON		1;
OFF		0;
h		1;
1		0;
x		.x. ;	" ABEL 'don't care' symbol
c		.C. ;	" ABEL 'clocking input' symbol

"Pin names:

"Control

clk2 oe

"Inputs pclk

wr

muxoe dramstart rasO ras1 refreq reset

"Outputs dramrdy ale cas refin rasOp ras1p qr

we

pin 1; "80386 Double-Frequency system clock pin 11; " Output Enable (tie active low)

pin 2; " system clock

pin 7; .. write/readit from 8111386

pin 6; " from dramp1 PLD pin 5; " from dramp1 PLD.

pin 4; " from drampl PLD pin 3; " from dramp1 PLD

pin 8; " from refresh counter pin 9;

pin 12; " READY for dram cycles pin 13; " Address latch enable pin 14; n cas for drams

pin 15; n refresh request to dramp1 PLD pin 16; " precharge counter to dramp1 PLD pin 17; " precharge counter to dramp1 PLD pin 18; "

pin 19; " write enable

Figure 8-3. DRAMP2 PLD Equations

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