Intel 386 manual Cache Coherency, Bus Watching

CACHE SUBSYSTEMS

•In a power failure, the data in the cache is lost, so there is no way to tell which locations of the main memory contain stale data. Therefore, the main memory as well as the cache must be considered volatile and provisions must be made to save the data in the cache in the case ofa power failure.

7.3.4Cache Coherency

Write-through and write-back eliminate stale data in the main memory caused by cache write operations. However, if caches are used in a system in which more than one device has access to the main memory (multi~processing systems or DMA systems, for exam- pie), another stale data problem is introduced. If new data is written to main memory by one device, the cache maintained by another devicewill contain stale data, A system that prevents the stale cache data problem is said to maintain cache coherency. Four cache coherency approaches are described below:

•Bus Watching (Snooping) - The cache controller monitors the system address lines when other masters are accessing shared memory. If another master writes to a loca~ tion in shared memory which also resides in the cache memory, the cache controller invalidates that cache entry. The 82385 uses snooping to maintain cache coherency in ~uIti-mastersystems. Figure 7-6 illustrates bus watching.

•Hardware transparency - Hardware guarantees cache coherency by ensuring that all accesses to memory mapped by a cache are seen by the cache. This is accomplished either by routing the accesses of all devices to the main memory through the same

OTHER BUS

MASTER

			~
1386'· OX CPU	•	..	82385

SHARED

MEMORY

231732i7·6

Figure 7-6. Bus Watching

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