PHYSICAL DESIGN AND DEBUGGING
One way to minimize this is by decreasing the lengths of the interconnections. Overall route lengths are shorter in multilayer
The guidelines discussed so far are prominent at higher operating frequencies. Debug- ging an Inte1386 DX
11.5 LATCH-UP
•Observe the maximum input voltage rating of I/O pins.
•Never apply power to Inte1386 DX processor pin or to any device connected to it before applying power to the Inte1386 DX processor.
•Use good termination techniques to prevent overshoot and undershoot.
•Ensure a proper layout to minimize reflections and to reduce noise on the signals.
11.6CLOCK CONSIDERATIONS
11.6.1 Requirements
For performance at high frequencies, the clock signal (CLK2) for the Intel386 DX microprocessor must be free of noise and within the specifications listed in the Intel386 DX microprocessor data sheet. These requirements can be met by following these guidelines:
•Construct the Clock Generating circuit as shown in Figure
•Terminate the CLK2 output to obtain a clean signal.
•Avoid placing too many loads on a single driver and carefully plan the traces to minimize reflection.
•Use an oscilloscope to verify the waveform of CLK2 against the specification in the Inte1386 DX microprocessor data sheet.