INTERNAL ARCHITECTURE
The Execution Unit in turn consists of three subunits:
• Control Unit
• Data Unit
• Protection Test Unit
Figure
2-2
shows the organization of these units. This chapter describes the function of
each unit, as well
as
interactions between units.
2.1
BUS
INTERFACE UNIT
The Bus Interface Unit provides the interface between the Inte1386
DX
microprocessor
and its environment.
It
accepts internal requests for code fetches (from the Code
Prefetch Unit) and data transfers (from the Execution Unit), and prioritizes the
requests.
At
the same time, it generates or processes the signals to perform the current
bus cycle. These signals include the address, data, and control outputs for accessing
external memory and I/O. The Bus Interface Unit also controls the interface to external
bus masters and coprocessors.
2.2 CODE PREFETCH UNIT
The Code Prefetch Unit performs the program look ahead function of the Inte1386
DX
microprocessor. When the Bus Interface Unit
is
not performing bus cycles to execute an
instruction, the Code Prefetch Unit uses the Bus Interface Unit to fetch sequentially
along the instruction byte stream. These prefetched instructions are stored in the 16-byte
Code Queue to await processing
by
the Instruction Decode Unit.
Code prefetches are given a lower priority than data transfers; assuming zero wait state
memory access, prefetch activity never delays execution. On the other hand, if there
is
no data transfer requested, prefetching uses bus cycles that would otherwise be idle.
Instruction prefetching reduces to practically zero the time that the processor spends
waiting for the next instruction.
2.3 INSTRUCTION DECODE UNIT
The Instruction Decode Unit takes instruction stream bytes from the Prefetch Queue
and translates them into microcode. The decoded instructions are then stored
in
a three-
deep Instruction Queue (FIFO) to await processing
by
the Execution Unit. Immediate
data and opcode offsets are also taken from the Prefetch Queue. The decode unit works
in
parallel with the other units and begins decoding when there
is
a free slot
in
the FIFO
and there are bytes in the prefetch queue. Opcodes can be decoded at a rate of one byte
per clock. Immediate data and offsets· can be decoded in one clock regardless of their
length.
2-2