Intel 386 manual Building and Debugging a System Incrementally

PHYSICAL DESIGN AND DEBUGGING

Also, after reset (until the Intel386 DX microprocessor executes an intersegment JMP or CALL instruction), the physical base address of the code segment is set internally to FFFFOOOOH. Therefore, the physical address of the first code fetch after reset is always FFFFFFFOH. The simple diagnostic program must begin at this location.

11.8.4 Building and Debugging a System Incrementally

When designing an Inte1386 DX microprocessor system, the designer plans the entire system. The core portions must be tested, however, before building the entire system. Beginning with only the Intel386 DX microprocessor and the clock generator, the following steps outline an approach that enables the designer to build up a system incrementally:

1.Install the clock generator. Check that the CLK2 signal is clean. Connect the CLK2 signal to the Intel386 DX microprocessor.

2.Connect the RESET output to the Intel386 DX microprocessor RESET input, and with CLK2 running, check that the state of the Intel386 DX microprocessor during RESET is correct.

3.Tie the Intel386 DX microprocessor INTR, NMI, and HOLD input pins low. Tie the READY# pin high so that the first bus cycle will not end. Reset the Inte1386 DX microprocessor, and check that the Inte1386 DX microprocessor is emitting the. correct signals to perform its first code fetch from physical address FFFFFFFOH. Connect the address latch, and verify that the address is driven at its outputs.

4.Connect the address decoding hardware to the Intel386 DX microprocessor, and check that after reset, the Inte1386 DX microprocessor is attempting to select the EPROM devices in which the initial code to be executed will be stored.

5.Connect the data transceiver to the system, and check that after reset, the trans- ceiver control pins are being driven for a read cycle. Connect all address pins of the EPROM sockets, and check that after reset, they are receiving the correct address for the first code fetch cycle.

Intel's iPPS programmer for EPROMs supports dividing an object module into four EPROMs, as is necessary for a 32-bit data bus to EPROM. The programmer can also divide an object module into two EPROMs for a 16-bit data bus to the EPROMs. (In this case, the BS16# input to the Intel386 DX microprocessor must be asserted during all bus cycles communicating with the EPROMs).

When the clock generator, Intel386 DX microprocessor, address decoder, address latch, data transceiver, and READY# generation logic (including wait-state generation) are functioning, the Inte1386 DX microprocessor is capable of running the software in the EPROMs. Now the simple debug program described above can be run to see whether the parts of the system work together.

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