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MUL Tibus II Intel386 OX Microprocessor
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Thermal Characteristics
Lattice Diagram
READY# Signal Timing
Logic Delay
Operating Mode Configurations
Reset
Simplest Diagnostic Program
Resolution
Power and Ground Planes
Domestic Service Offices
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Image 201
MUL TIBUS II and
1
0
Intel386 OX Microprocessor
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Page 202
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Image 201
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Contents
Page
Current Handbooks
Infel
Canada Literature Order Form
Name Company ~ Address City State ZIP Country
International Literature Order Form
Microprocessor Hardware Reference Manual
Intel Corporation 1986 CG-072391
Customer Support
Intels Complete Support Solution Worldwide
Page
Related Publications
Preface
Organization of this Manual
Preface
Page
Table of Contents
Chapter Performance Considerations
Chapter Cache Subsystems
Chapter
Table of Contents Chapter Physical Design and Debugging
Figures
Figures
In.teI
System Overview
Page
Microprocessor
Chapter System Overview
Lntel386 OX Microprocessor System Block Diagram
Micro Channel-Compatible Solution with 82311 Chip Set
Integrated System Peripheral
Coprocessors
Cache Controller
Eisa Chip SET
LAN Coprocessor
Clock Generator
8086/80286 Family Components
Intel Programmable Logic Devices
Internal Architecture
Page
Chapter Internal Architecture
BUS Interface Unit
Code Prefetch Unit
Instruction Decode Unit
=i m
Execution Unit
Segmentation Unit
Paging Unit
Local Bus Interface
Page
Chapter Local BUS Interface
BUS Operations
Bus States
Summary of Intel386 OX Microprocessor Signal Pins
ClK2and ClK Relationship
CLK2 nIUrL1lrtn-rtn-rtn-rtn-rtn-rtfLrtn-n.rurL1l
3 32-Bit Data Bus Transfers and Operand Alignment
Address Pipelining
Local BUS Interface
Consecutive Bytes in Hardware Implementation
Possible Data Transfers to 32-Bit Memory
Misaligned Transfer
Read Cycle
Non-Pipelined Address Read Cycles
Pipelined Address Cycle
Write Cycle
Non-Pipelined Address Write Cycles
~~r-...............-r--+-----r-------r-.......~---f\j~~
Interrupt Acknowledge Cycle
Halt/Shutdown Cycle
JUlrutrutrulrutrutrutillh.Ilrutruln.n
9 8516 Cycle
13 compares the signals for 32-bit and 16-bit bus cycles
10 i6-Bit Byte Enables and Operand Alignment
13 -Bit and 16-Bit Bus Cycle Timing
DIS-DO
LOCALBU51NTERFACE
BUS Timing
READY# Signal Timing
Clock Timing
Clock Generation
16.Clock Generator
Crystal Oscillator Clock Generator
17. ADS# Synchronizer
Interrupts
Non-Maskable Interrupt NMI
Interrupt Latency
Maskable Interrupt Intr
Locked Cycle Activators
BUS Lock
Locked Cycle Timing
EJj
HOLD/HLDA Hold Acknowledge
LOCK# Signal Duration
HOLD/HLDA Timing
Hold Signal Latency
Reset Timing
Reset
Hold State Pin Conditions
Intel386 OX Microprocessor Internal States
RES# ~----------5S 5 mml
Performance Considerations
Page
Wait States and Pipelining
Chapter Performance Considerations
Wait States
Performance versus Wait States and Operating Frequency
Page
Coprocessor Hardware Interface
Page
Chapter Coprocessor Hardware Interface
Intel387 OX Math Coprocessor Connections
Intel387 OX Math Coprocessor Interface
InteI386OX CPU System with Intel387MOX Math Coprocessor
Intel387 OX Math Coprocessor Clock Input
Intel387 OX Math Coprocessor Bus Cycles
CLK2
Local BUS Activity with the Intel387 OX Math Coprocessor
80287/lnte1387 OX Math Coprocessor Recognition
Hardware Recognition of the NPX
Software Recognition of the NPX
Software Routine to Reco.gnize the Coprocessor
Coprocessor .HARDWARE Interface
Memory Interfacing
Page
Chapter Memory Interfacing
Memory Speed Versus Performance and Cost
Basic Memory Interface
TTL Devices
Flb
Common Logic Families
PLD Devices
Memory Interfacing
=8=
Address Decoder
Address Latch
Bus Control Logic
Data Transceiver
~~Y
Eprom Interface
Nanosecond Eprom Timing Diagram
8 16-Bit Interface
Interleaved Memory
Dynamic RAM Dram Interface
Dram Memory Performance
Dram Memory Performance
3.1 3-ClK Dram CONTROllER
Dram Controller
IIII~
DRAMP2
Memory Interfacing
~1\
ClK Y Y \JY
Dram Timing Analysis
Logic Delay
= 50 30 6 +
+ 3 +
Avoiding Data BUS Contention
Control Signal Timings
Logic Paths
Dram Design Variations
Using TAP Delay Lines
Refresh Cycles
5.2 BUR&T Refresh
Initialization
Cache Subsystems
Page
Cache Memory System
Chapter Cache Subsystems
Introduction to Caches
Program Locality
Block Fetch
Fully Associative Cache
Cache Organizations
Direct Mapped Cache
Direct Mapped Cache Organization
Set Associative Cache
Cache Subsystems
Cache Updating
Write-Through System
Buffered Write-Through System
3B6oOX CPU -u
Write-Back System
Bus Watching
Cache Coherency
Hardware Transparency
Efficiency and Performance
Non-Cacheable Memory
Cache and DMA
Cache Example
Example Design
Example Cache Memory Organization
Example of Cache Memory Organization
Bus Structure with
11. Intel386 OX Microprocessor/82385 System Bus Structure
2 82385/lnte1386 OX Microprocessor Interface
12. Intel386 OX Microprocessor/82385 Interface
2.3 82385 System Configuration Inputs
13.Direct Mapped Cache without Data Buffers
3 82385 Cache Organiza~ion
~~~~----------~~
74AS~~ x~- ~ CWEB#
Write Cycles
Special Design Notes
System Interface
Cache Subsystems
Page
Interfacing
Page
Chapters Interfacing
I/O Mapping Versus Memory Mapping
8-BIT, 16-BIT, and 32-BIT I/O Interfaces
2 8-Bit I/O
Address Decoding
Interfacing
4 32-Bit I/O
3 16-Bit I/O
Linear Chip Selects
Basic I/O Interface
Address Latch
~ #1
TTT
111tJI
Timing Analysis for I/O Operations
\.LI,1l
Xcvr. prop Min
1 8274 Serial Controller
Basic I/O Examples
2 82380 Programmable Interrupt Controller
3 8259A Interrupt Controller
#- IRS
Cascaded Interrupt Controllers
80286-COMPATIBLE BUS Cycles
1 AO/A1 Generator
2 SO#/S1 # Generator
O21
DIC. --t-~=r-\---+---.J
Bus Controller and Bus Arbiter
6 82586 LAN Coprocessor
5 82380 Integrated System Peripheral
·13. Intel386 OX Microprocessor/82380 Interface
14. LAN Station
Dedicated CPU Decou Pled DUAL-PORT Memory
Coupled DUAL-PORT Memory
17. Shared Bus Interface
MULTIBUSland9 Intel386 ox Microprocessor
Page
Multi BUS I and Intel386 DX Microprocessor
Chapter
Address Latches and Data Transceivers
Multibus I Interface Example
BUS
·2. Multibus I Address Latches and Data Transceivers
Wait-State Generator
Wait-State Generator Logic
BUSY#
Ex L-lLS
Pcb
Timing Analysis of Multibus I Interface
2 82289 Operating Modes
Priority Resolution
Bus Priority Resolution
Operating Mode Configurations
Multibus I Locked Cycles
Other Multibus I Design Considerations
Interrupt-Acknowledge on Multibus
Byte Swapping during Multibus I Byte Transfers
»-+-J¢l~~~
ALE~
Bus Timeout Function for Multibus I Accesses
Multibus I Power Failure Handling
~----I~
Avoiding Deadlock with Dual-Port RAM
DUAL-PORT RAM with Multibus
MUL Tibus II Intel386 OX Microprocessor
Page
Parallel System BUS iPSB
Multibus II Standard
Shows how the timing of these cycles overlap
IPSB Bus Cycle Timing
IPSB Bus Interface
IPSe Interface
10-5
MIC Signals
Serial System BUS iSSB
Local BUS Extension iLBX
Page
Physical Design
Page
Power Dissipation and Distribution
Chapter Physical Design and Debugging
General Design Guidelines
Power and Ground Planes
EMI, which will be discussed in Section
Decoupling Capacitors
Roo
GNO
Sx/1
Physical Design and Debugging
High Frequency Design Considerations
~O~
Transmission Line Effects
+1~
+~---------Dielectric
Impedance Mismatch
~~---T-ime---~--~~~=
10. Loaded Transmission Line
+ TI Vst-tpd2L-xHt-tpd 2L-x + TITs Vst-tpd2L+x Ht-tpd2L+x
11. Lattice Diagram
~.-----..-.r Tpo 3.02
Need for Termination
NVv
Thevenins Equivalent Termination
·15. Thevenins Equivalent Circuit
1111
Impedance Matching Example
Daisy Chaining
20. Daisy Chaining
Interference
Electromagnetic Interference CROSS-TALK
22. Typical Layout
23. Closed Loop Signal Paths are Undesirable
Propagation Delay
LATCH-UP
Clock Considerations
Requirements
·24. Typical Intel386 DX Microprocessor Clock Circuit
Routing
Physical Design and Debugging
27. Star Connectipn
Thermal Characteristics
Debugging Considerations
Hardware Debugging Features
Bus Interface
Ffffo
Simplest Diagnostic Program
Building and Debugging a System Incrementally
Other Simple Diagnostic Software
EQU
Debugging Hints
30. Object Code for Diagnostic Program
Test Capabilities
Page
Chapter Test Capabilities
Internal Tests
Automatic Self-Test
TLR
Translation Lookaside Buffer Tests
Bit Name Definition
Test Capabilities
BOARD..LEVEL Tests
Page
Local Bus Control PLD Descriptions
Page
Appendix a Local BUS Control PLD Descriptions
IOPLD1 Functions
IOPLD2 Functions
PLD Equations
Figure A-1. IOPLD1Equations
Figure A-1. IOPLD1 Equations Contd
Figure A·1. IOPLD1 Equations Contd
IIIIIIIIIInllllIIIIIIIIIIIIII
Figure A-2. IOPLD2 Equations Contd
Figure A-2. IOPLD2 Equations Contd
Iowr
Figure A-3. RESET/CLOCK PLD Equations
Figure A-3. RESET/CLOCK PLDEquations Contd
Figure A-3. RESET/CLOCK PLD Equations Contd
Dram PLD Descriptions
Page
Dram PLDs
Appendix B Dram PLD Descriptions
IUIIIIII11111111111111
DRAMP1 PLD Equations Contd
Figure B-2. DRAMP1 PLD Equations Contd
Figure B·2. DRAMP1 PLD Equations Contd
DRAMP1 PLD Equations Contd
DRAMP2 PLD Equations
Figure B·3. DRAMP2 PLD Equations Contd
Infel
In+-I
Figure B-3. DRAMP2 PLD Equations Contd
Refresh Address Counter PLD Pin Description
Refresh Address Counter PLD
Refresh Address Counter PLD Equations
In+-I
RAS
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