Intel 386 manual 10-5

MULTIBUS II AND Intel386 DX MICROPROCESSOR

The BAC signals can be divided into three functional groups:

•iPSB interface

•Local bus interface

•Register interface with the Inte1386 DX microprocessor

The iPSB interface signals perform mainly arbitration and system control. Five bidirec- tional Arbitration signals (ARBS-ARBO) are used during reset to read a cardslot ID and arbitration ID from the CSM, and during arbitration cycles to output the arbitration ID for priority resolution. Bus Request (BREQ#) is a bidirectional signal. Each bus agent asserts BREQ# to request control of the bus and samples BREQ# to determine if other agents are also contending for bus control.

Bus Error (BUSERR#) is a bidirectional signal that a bus agent outputs to all other bus agents when it detects a parity error during a transfer cycle. Bus Timeout (TIMOUT #) is output by the CSM to all bus agents when a bus cycle fails to end within a prescribed time period.

Ten System Control signals (SC9#-SCO#) coordinate transfer cycles. The MULTIBUS® II Architectural Specification defines each of these signals. Directional enables (SCOEH and SCOEL) are provided for transceivers to buffer these bidirec- tional signals. External logic checks byte parity on the multiplexed address and data bus (AD31-ADO) and sets the Parity inputs (PAR3-PARO) accordingly.

Other iPSB signals are Reset (RST#), Reset-Not-Complete (RSTNC#), and ID Latch (LACHn#, n = slot number). These signals are used only during reset.

Local bus interface signals pertain to the communication between the BAC and the Inte1386 DX microprocessor or between the BAC and the MIC. These signals indicate to the BAC when to request bus control and what type of bus cycle to drive when it gains bus control.

Four control signals are necessary for each of the two devices connected to the BAC. The signals that connect to the Inte1386 DX microprocessor are REQUESTA, GRANTA, READYA, and S;ELECTA; those that connect to the MIC are REQUESTB, GRANTB, READYB, and SELECTB.

To request bus control, the Intel386 DX microprocessor or the MIC activates one of the REQUEST signals. The corresponding GRANT signal is returned by the BAC when it has bus control. Data width and address space selections are encoded on the WIDTHl#, WIDTHO#, SPACEl#, and SPACEO# inputs, whileWR# dictates either a write cycle or a read cycle. These five inputs translate directly to SC6#-SC2# outputs during the request phase of a transfer cycle. READYA or READYB indicates that WIDTHO#, WIDTHl#, SPACEO#, SPACEl#, and WR# can be read by the BAC to drive the transfer cycle.

LASTINA or LASTINB controls the end-of-cycle signal for burst transfers. The LOCK# input is activated for locked transfers.

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