MULTIBUS II AND Intel386 DX MICROPROCESSOR
The BAC signals can be divided into three functional groups:
•iPSB interface
•Local bus interface
•Register interface with the Inte1386 DX microprocessor
The iPSB interface signals perform mainly arbitration and system control. Five bidirec- tional Arbitration signals
Bus Error (BUSERR#) is a bidirectional signal that a bus agent outputs to all other bus agents when it detects a parity error during a transfer cycle. Bus Timeout (TIMOUT #) is output by the CSM to all bus agents when a bus cycle fails to end within a prescribed time period.
Ten System Control signals
Other iPSB signals are Reset (RST#),
Local bus interface signals pertain to the communication between the BAC and the Inte1386 DX microprocessor or between the BAC and the MIC. These signals indicate to the BAC when to request bus control and what type of bus cycle to drive when it gains bus control.
Four control signals are necessary for each of the two devices connected to the BAC. The signals that connect to the Inte1386 DX microprocessor are REQUESTA, GRANTA, READYA, and S;ELECTA; those that connect to the MIC are REQUESTB, GRANTB, READYB, and SELECTB.
To request bus control, the Intel386 DX microprocessor or the MIC activates one of the REQUEST signals. The corresponding GRANT signal is returned by the BAC when it has bus control. Data width and address space selections are encoded on the WIDTHl#, WIDTHO#, SPACEl#, and SPACEO# inputs, whileWR# dictates either a write cycle or a read cycle. These five inputs translate directly to
LASTINA or LASTINB controls the