LOCAL BUS INTERFACE
3.6.3 HOLD State Pin Conditions
LOCK#, M/IO#, D/C#, W/R#, ADS#, A31-A2, BE3#-BEO#, and D31-DO enter the three-state OFF condition in the HOLD state. Note that external pullup resistors may be required on ADS#, LOCK# and other signals to guarantee that they remain inactive during transitions between bus masters.
3.7 RESET
RESET starts or restarts the Inte1386 DX microprocessor. When the Intel386 DX micro- processor detects a low-to-high transition on RESET, it terminates all activities. When RESET goes low again, the Intel386 DX microprocessor is initialized to a known inter- nal state and begins fetching instructions from the reset address.
3.7.1 RESET Timing
The clock generator generates the RESET signal to initialize the Inte1386 DX micropro- cessor and other system components.
The RESET input of the Intel386 DX microprocessor must remain high for at least 15 CLK2 periods to ensure proper initialization (at least 80 CLK2 periods if self-test is to be performed). The CLK output of the clock generator is initialized with the rising edge of RESET. When RESET goes low, the Inte1386 DX microprocessor adjusts the falling edge of its internal clock (CLK) to coincide with the start of the first CLK2 cycle after the high-to-Iow transition of RESET. The clock generator times the high-to-Iow edge of RESET (synchronous to CLK2) so that the phase of the internal CLK of the Inte1386 DX microprocessor matches the phase of the CLK output of the clock generator. This relationship is shown in Figure 3-21.
On the high-to-Iow transition of RESET, the BUSY# pin is sampled. If BUSY# is low, the Inte1386 DX microprocessor will perform a self-test lasting approximately 220 + 60 CLK2 cycles before it begins executing instructions. The· Inte1386 DX microprocessor continues with initialization after the test, regardless of the test results.
The Intel386 DX microprocessor fetches its first instruction from linear address OFFFFFFFOH, sometime between 350 and 450 CLK2 cycles after the high-to-Iow tran- sition of RESET (or, if self-test is performed, after completion of self-test). Because paging is disabled, linear address OFFFFFFFOH is the same as physical address OFFFFFFFOH. This location normally contains a JMP instruction to the beginning of the bootstrap program.
3.7.2 Intel386 OX Microprocessor Internal States
RESET should be kept high for at least one millisecond after Vee and CLK2 have reached their DC and AC specifications.
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