Intel 386 manual 2 82380 Programmable Interrupt Controller, Interface

I/O INTERFACING

		8274
FROM DATA	D7-DO	DB7-DBO
TRANSCEIVER
FROM ADDRESS	(A3	Al
LATCH	A2	AO
		MODEM INTERFACE
FROM
ADDRESS	SERIO#	CS#
DECODER
FROM BUS	(RDN	RDN
CONTROLLER	WRN	WRH

231732i8-6

Figure 8-6. 8274 Interface

8.5.2 82380 Programmable Interrupt Controller

The 82380 Programmable Interrupt Controller (PIC) can be used in interrupt-driven microcomputer systems. It has 15 external and 5 internal interrupt requests. Each of the external requests can be cascaded with an additional 82C59A Interrupt Controller to accommodate up· to 120 external interrupt sources.

The 82380 PIC handles interrupt priority resolution and returns a preprogrammed ser- vice routine vector to the Intel386 DX microprocessor during an interrupt acknowledge cycle. It consists of three 82C59A compatible banks. The 82380 Data Sheet contains detailed information on the 82380 PIC.

When an interrupt occurs, the 82380 PIC activates its Interrupt (INT) output, which is connected to the Interrupt Request (INTR) input of the Inte1386 DX microprocessor. The Intel386 DX microprocessor automatically executes two back-to-back interrupt acknowledge cycles, as described in Chapter 3. The 82380 PIC will automatically termi- nate the interrupt acknowledge cycles by driving its READYO# signal. Each acknowl- edge cycle will be extended by five wait states. Also, four idle states are inserted by the Intel386 DX microprocessor between two consecutive interrupt acknowledge cycles.

8.5.2.1 CASCADED INTERRUPT CONTROLLERS TO THE 82380 PIC

Each of the external requests of the 82380 PIC can be cascaded with one 'slave' 82C59A Interrupt Controller. With all its external requests cascaded, the 82380 PIC can handle up to 120 external requests.

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