Intel 386 manual Efficiency and Performance, Hardware Transparency

CACHE SUBSYSTEMS

cache or by copying all cache writes both to the main memory and to all other caches that share the same memory (a technique known as broadcasting). Hardware trans- parent systems are illustrated in Figure 7-7.

•Non-cacheable memory - Cache coherency is maintained by designating shared memory as non-cacheable. In such a system, all accesses to shared memory are cache misses, because the shared memory is never copied into the cache. The non-cacheable memory can be identified using chip-select logic or high-address bits. Figure 7-8 illus- trates non-cacheable memory.

Software can offset the reduction in the hit rate caused by non-cacheable memory by using the string move instruction (REP MOVS) to copy data between non-cacheable memory and cacheable memory and by mapping shared memory accesses to the cacheable locatio~s. This technique is especially appropriate for systems in which copying is necessary for other reasons (as in some implementations of UNlX for example).

•Cache flushing - A cache flush writes any altered data to the main memory (if this has not been done with write-through) and clears the contents of the cache. If all the caches in the system are flushed before a device writes to shared memory, the poten- tial for stale data in any cache is eliminated.

Combinations of various cache coherency techniques may offer the optimal solution for a particular system. For example, a system might use hardware transparency for time- critical 110 operations such as paging and non-cacheable memory for slower I/O such as printing.

7.4 EFFICIENCY AND PERFORMANCE

The measurement of cache effectiveness is divided into two topics: efficiency and per- formance. Cache efficiency is its ability to maintain the most used code and data requested by the microprocessor. Efficiency is measured in terms of hit rate. Perfor- mance is a measurement of the speed in which a microprocessor can perform a given

OTHER
BUS	CACHE
MASTER	J,	MAIN
		MEMORY
i3B6~ OX	CACHE -
CPU

231732i7-7

Figure 7-7.Hardware Transparency

7-11