Intel 386 manual EMI, which will be discussed in Section

PHYSICAL DESIGN AND DEBUGGING

high-performance systems. Logic designers can use techniques designed to minimize this problem. One technique is to reduce capacitance loading on signal lines and provide optimum power and ground planes.

Power and ground lines have inherent inductance and capacitance, which affect the total impedance of the entire system. Higher impedances reduce current and therefore offer reduced power consumption, while low impedances (ground planes) help minimize prob- lems like noise and cross talk. Hence, it is very important for a designer to have a controlled impedance design where high speed signals are involved. The formula for impedance is as follows:

'Impedance= (ljC)1/2.

The total characteristic impedance for the power supply can be reduced by adding more lines. For multi-layer boards, power and ground planes must be used in the Inte1386 DX microprocessor designs.

The effect of adding more lines to reduce impedance is illustrated in Figure 11-1 which shows that two lilies in parallel have half the impedance of a single line.

To reduce impedance even further, more lines should be added. To lower the imped- ance, an infinite number of lines or a plane should be used. Planes also provide the best distribution of power and ground.

The Intel386 DX microprocessor has 20 power (Ved and 21 ground (Vss) pins. All power and ground pins must be connected to their respective planes. IdealJy, the Inte1386 DX microprocessor should be placed at the center of the board to take full advantage of these planes. Although Inte1386 DX CPU generally demands less power than the conventional devices, the possibility of power surges is increased due to proces- sors higher operating frequency and its wide address and data buses. Peak-to-peak noise on Vee relative to Vss should be maintained at no more than 400 mY, and preferably to no more than 200 mV.

Although power and ground planes are preferable to power and ground traces, double- layer boards present a need for routing of the power and ground traces.

'The inductive effect of a printed-circuit board (PCB) trace can be reduced by bypassing (or decoupling). Careful layout procedures should be observed to minimize inductances. Figure 11-2 shows methods for reducing the inductive effects of PCB traces. The power and ground trace layout has a low series inductance as shown in Figure 11-2. This is because the loop area between the integrated circuits (lCs) and the decoupling capaci- tors is small and the power and ground traces are closer. This results in lower character- istic impedance, which in turn reduces the line voltage drop.

Another placement technique is called orthogonal arrangement, which requires more area than the previous technique but produces similar results. This arrangement is shown in Figure 11-3. These techniques also reduce the electromagnetic interference

(EMI), which will be discussed in Section 11.3.3.1.	'
11-3