Intel 386 manual O21

I/O INTERFACING

BEDI

			l			H
		l	l	x	Ii	l	l		BEDI	[)o---{>o21
BE21			L	l	'~.	l	H	BE3I
									BEll
			l	x	If	l	l		---		Al
			x	x	Ii	x
		H
			l	H		l
				BEll
K-map for A1 signal
				BEDI
			l		H
		l	l	x	l	l	l		BEll
			l	.x:	H	l					HE
BE21							H	BE31	BE31
		H	l	H	:x	l			----..-
			x	x	l	x	l
			l	H		l
				BEll
K-map for l6-bit BHE# signal
	BEDI
	l		H
l	x	l	H	l
l	x	l	.H
l					BE31
BE21	l	X' H		H
l
H	x	H	.x	l
x

l H l

BEll

K-map for lS-bit BlE # signal

231732i8-9

Figure 8-9. AO, A1, and BHE# Logic

cycle, and the PLD READY# output uses these signals to set READY# active after the required number of wait states. Two of the wait-state signals, WSI and WS2, are also used to generate SO# and Sl#,:as shown in Figur\! 8-10.

The PCLK signal, which necessary for producing 80286-compatible wait states, isgener- ated by dividing the CLK signal from the 82384 by two.

To meet the READY# input hold time 'requirement (25 nanoseconds) for the 82288 Bus Controller, the. READY# signal must be two CLK cycles long. Therefore, two PLD equations are required to generate READY#. The first equation generates the Ready Pulse (RDYPLSE) output. RDYPLSE is fed into the READY# equation to extend READY# by an additional CLK cycle. These signals are gated by PCLK.

RDYPLSE : = ARDY * PCLK

/READY : = ARDY * PCLK + RDYPLSE

8-19