Intel manual Lntel386 OX Microprocessor System Block Diagram

SYSTEM OVERVIEW

CLOCK

GENERATOR

CLK2
1386" OX	1387'·OX
MICRO·	MATH
PROCESSOR	COPROCESSOR

CACHE	82835	82370	82596 OX
	CACHE		LAN
MEMORY	CONTROLLER	OMA	COPROCESSOR

MAINPERIPHERALS

MEMORY

231732i1-1

Figure 1-1. l"ntel386™ OX Microprocessor System Block Diagram

in detail in Chapter 2. Because the Intel386 DX microprocessor prefetches instructions and queues them internally, instruction fetch and decode times are absorbed in the pipeline; the processor rarely has to wait for an instruction to execute.

Pipelining is not unusual in modern microprocessor architecture; however, including the memory management unit (MMU) in the on-chip pipeline is a unique feature of the Intel386 DX Architecture. By performing memory management on-chip, the Intel386 DX microprocessor eliminates the serious access delays typical of implementa- tions that use off-chip memory management units. The benefit is not only high perfor- mance but also relaxed memory-access time requirements, hence lower system cost.

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