Intel 386 manual Cache and DMA, Cache Example, Example Design

CACHE SUBSYSTEMS

7.5 CACHE AND DMA

Cache coherency is an issue one must consider when placing a DMA controller in an Intel386 DX microprocessor system. Because the DMA controller has access to main memory, it can potentially introduce stale data. As was mentioned before, stale data can be avoided in the following ways:

oImplementing bus watching (snooping). In this approach, the DMA controller writes to main memory, and the cache controller monitors DMA cycles and automatically invalidates any cache location altered by DMA.

oImplementing a transparent cache, in which memory accesses from both the Inte1386 DX microprocessor and the DMA controller are directed through the cache.

•Restrict DMA cycles to non-cacheable areas of memory.

The first method has a distinct advantage: since the DMA controller does not access the cache directly, the Intel386 DX microprocessor can read from the cache while the DMA controller is moving data to the main memory. Although bus watching is difficult to implement in a discrete cache design, the 82385 integrates this function and performs zero waitstate bus watching. The overall memory bandwidth is increased since the Intel386 DX microprocessor can access its cache at the same time as the DMA control- ler accesses main memory.

The second approach has the advantage of requiring minimal hardware, but has the disadvantage that the Intel386 DX microprocessor must be placed in HOLD during DMA transfers. The third approach is useful if a separate, dual-ported memory can be used as the non-cache able memory, and the DMA device is tightly coupled to this mem- ory. In all approaches, the cache should be made software transparent, so that DMA cycles do not require special actions by software to insure cache coherency.

7.6 CACHE EXAMPLE

The cache system example described in this section illustrates some of the decisions a cache designer must make. The requirements of a particular system may result in differ- ent choices than the ones made here. However, the issues presented in this section will arise in the process of designing any cache system.

7.6.1 Example Design

The cache system uses a direct-mapped cache. In previous generations of computers, it was often practical to build a 2-way or 4-way associative cache. SRAMs had low memory capacity, so many of them were needed to construct a cache of reasonable size. However, today's SRAMs are more dense, cost less, and take up less space. It is now more eco- nomical to increase cache efficiency by increasing cache size (SRAMs) rather than asso- ciativity (control logic and comparators).

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