MULTIBUS I AND Intel386 OX MICROPROCESSOR
SERIAL PRIORITY RESOLVING TECHNIQUE
| | 1 |
74146 | 74136 | ; |
PRIORITY | 3T06 | |
4 ENCODER | DECODER | 4 |
PARALLEL PRIORITY RESOLVING TECHNIQUE
231732i9-7
Figure 9-7. Bus Priority Resolution
In addition, the bus arbiter can switch between modes 2 and 3, based on the type of bus cycle.
Figure 9-8 shows the strapping configurations required to implement each of these four techniques.
The operating mode of one bus arbiter affects the throughput of both the individual subsystem as well as other subsystems on MULTIBUS I. This is because the delay required to transfer MULTIBUS I control from one bus arbiter to another affects all
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