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Intel 386 manual Physical Design

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Thermal Characteristics Lattice Diagram READY# Signal Timing Logic Delay Operating Mode Configurations Reset Simplest Diagnostic Program Resolution Power and Ground Planes Domestic Service Offices

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Physical Design and

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Debugging

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Intel 386 manual Physical Design

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Contents

Page Current Handbooks InfelCanada Literature Order Form Name Company ~ Address City State ZIP Country International Literature Order FormMicroprocessor Hardware Reference Manual Intel Corporation 1986 CG-072391 Customer Support Intels Complete Support Solution WorldwidePage Related Publications PrefaceOrganization of this Manual Preface Page Table of Contents Chapter Performance Considerations Chapter Cache Subsystems Chapter Table of Contents Chapter Physical Design and Debugging Figures Figures In.teI System Overview Page Microprocessor Chapter System OverviewLntel386 OX Microprocessor System Block Diagram Micro Channel-Compatible Solution with 82311 Chip Set Integrated System Peripheral CoprocessorsCache Controller Eisa Chip SET Clock Generator LAN Coprocessor8086/80286 Family Components Intel Programmable Logic Devices Internal Architecture Page Chapter Internal Architecture Code Prefetch Unit BUS Interface UnitInstruction Decode Unit =i m Segmentation Unit Execution UnitPaging Unit Local Bus Interface Page Chapter Local BUS Interface BUS Operations Bus States Summary of Intel386 OX Microprocessor Signal PinsClK2and ClK Relationship CLK2 nIUrL1lrtn-rtn-rtn-rtn-rtn-rtfLrtn-n.rurL1l 3 32-Bit Data Bus Transfers and Operand Alignment Address PipeliningLocal BUS Interface Consecutive Bytes in Hardware Implementation Possible Data Transfers to 32-Bit Memory Misaligned Transfer Read Cycle Non-Pipelined Address Read Cycles Pipelined Address Cycle Write CycleNon-Pipelined Address Write Cycles ~~r-...............-r--+-----r-------r-.......~---f\j~~ Interrupt Acknowledge Cycle Halt/Shutdown Cycle JUlrutrutrulrutrutrutillh.Ilrutruln.n9 8516 Cycle 13 compares the signals for 32-bit and 16-bit bus cycles 10 i6-Bit Byte Enables and Operand Alignment13 -Bit and 16-Bit Bus Cycle Timing DIS-DO LOCALBU51NTERFACE BUS Timing READY# Signal Timing Clock Timing Clock Generation16.Clock Generator Crystal Oscillator Clock Generator17. ADS# Synchronizer InterruptsNon-Maskable Interrupt NMI Interrupt Latency Maskable Interrupt IntrLocked Cycle Activators BUS LockLocked Cycle Timing EJjHOLD/HLDA Hold Acknowledge LOCK# Signal DurationHOLD/HLDA Timing Hold Signal Latency Intel386 OX Microprocessor Internal States ResetReset Timing Hold State Pin ConditionsRES# ~----------5S 5 mml Performance Considerations Page Wait States and Pipelining Chapter Performance ConsiderationsWait States Performance versus Wait States and Operating Frequency Page Coprocessor Hardware Interface Page Chapter Coprocessor Hardware Interface Intel387 OX Math Coprocessor Connections Intel387 OX Math Coprocessor InterfaceInteI386OX CPU System with Intel387MOX Math Coprocessor Intel387 OX Math Coprocessor Clock Input Intel387 OX Math Coprocessor Bus CyclesCLK2 Local BUS Activity with the Intel387 OX Math CoprocessorHardware Recognition of the NPX 80287/lnte1387 OX Math Coprocessor RecognitionSoftware Recognition of the NPX Software Routine to Reco.gnize the Coprocessor Coprocessor .HARDWARE Interface Memory Interfacing Page Memory Speed Versus Performance and Cost Chapter Memory InterfacingBasic Memory Interface TTL Devices FlbCommon Logic Families PLD DevicesMemory Interfacing =8= Address Decoder Address LatchBus Control Logic Data Transceiver~~Y Eprom Interface Nanosecond Eprom Timing Diagram 8 16-Bit Interface Interleaved Memory Dynamic RAM Dram InterfaceDram Memory Performance Dram Memory Performance3.1 3-ClK Dram CONTROllER Dram ControllerIIII~ DRAMP2 Memory Interfacing ~1\ ClK Y Y \JYDram Timing Analysis Logic Delay = 50 30 6 + + 3 + Avoiding Data BUS Contention Control Signal Timings Logic Paths Dram Design Variations Using TAP Delay Lines Refresh Cycles 5.2 BUR&T Refresh Initialization Cache Subsystems Page Cache Memory System Chapter Cache SubsystemsProgram Locality Introduction to CachesBlock Fetch Fully Associative Cache Cache OrganizationsDirect Mapped Cache Direct Mapped Cache Organization Set Associative Cache Cache Subsystems Write-Through System Cache UpdatingBuffered Write-Through System 3B6oOX CPU -u Write-Back SystemBus Watching Cache CoherencyHardware Transparency Efficiency and PerformanceNon-Cacheable Memory Cache Example Cache and DMAExample Design Example Cache Memory Organization Example of Cache Memory Organization Bus Structure with 11. Intel386 OX Microprocessor/82385 System Bus Structure 2 82385/lnte1386 OX Microprocessor Interface12. Intel386 OX Microprocessor/82385 Interface 2.3 82385 System Configuration Inputs 13.Direct Mapped Cache without Data Buffers 3 82385 Cache Organiza~ion~~~~----------~~ 74AS~~ x~- ~ CWEB# Write Cycles Special Design Notes System InterfaceCache Subsystems Page Interfacing Page I/O Mapping Versus Memory Mapping Chapters Interfacing8-BIT, 16-BIT, and 32-BIT I/O Interfaces 2 8-Bit I/O Address DecodingInterfacing Basic I/O Interface 3 16-Bit I/O4 32-Bit I/O Linear Chip SelectsAddress Latch ~ #1 TTT 111tJI Timing Analysis for I/O Operations \.LI,1l Xcvr. prop Min 1 8274 Serial Controller Basic I/O Examples2 82380 Programmable Interrupt Controller 3 8259A Interrupt Controller #- IRSCascaded Interrupt Controllers 80286-COMPATIBLE BUS Cycles 1 AO/A1 Generator 2 SO#/S1 # Generator O21 DIC. --t-~=r-\---+---.J Bus Controller and Bus Arbiter6 82586 LAN Coprocessor 5 82380 Integrated System Peripheral·13. Intel386 OX Microprocessor/82380 Interface 14. LAN Station Dedicated CPU Decou Pled DUAL-PORT Memory Coupled DUAL-PORT Memory 17. Shared Bus Interface MULTIBUSland9 Intel386 ox Microprocessor Page Multi BUS I and Intel386 DX Microprocessor ChapterAddress Latches and Data Transceivers Multibus I Interface ExampleBUS ·2. Multibus I Address Latches and Data Transceivers Wait-State Generator Wait-State Generator Logic BUSY# Ex L-lLS Pcb Timing Analysis of Multibus I Interface 2 82289 Operating Modes Priority ResolutionBus Priority Resolution Operating Mode Configurations Other Multibus I Design Considerations Multibus I Locked CyclesInterrupt-Acknowledge on Multibus Byte Swapping during Multibus I Byte Transfers »-+-J¢l~~~ ALE~ Bus Timeout Function for Multibus I AccessesMultibus I Power Failure Handling ~----I~ Avoiding Deadlock with Dual-Port RAM DUAL-PORT RAM with MultibusMUL Tibus II Intel386 OX Microprocessor Page Parallel System BUS iPSB Multibus II StandardShows how the timing of these cycles overlap IPSB Bus Cycle Timing IPSB Bus Interface IPSe Interface10-5 MIC Signals Serial System BUS iSSB Local BUS Extension iLBXPage Physical Design Page Chapter Physical Design and Debugging Power Dissipation and DistributionGeneral Design Guidelines Power and Ground Planes EMI, which will be discussed in Section Decoupling Capacitors RooGNO Sx/1 Physical Design and Debugging High Frequency Design Considerations ~O~Transmission Line Effects +1~ +~---------Dielectric Impedance Mismatch ~~---T-ime---~--~~~=10. Loaded Transmission Line + TI Vst-tpd2L-xHt-tpd 2L-x + TITs Vst-tpd2L+x Ht-tpd2L+x 11. Lattice Diagram ~.-----..-.r Tpo 3.02 Need for Termination NVv Thevenins Equivalent Termination ·15. Thevenins Equivalent Circuit 1111 Impedance Matching Example Daisy Chaining 20. Daisy Chaining InterferenceElectromagnetic Interference CROSS-TALK 22. Typical Layout 23. Closed Loop Signal Paths are Undesirable Propagation Delay Clock Considerations LATCH-UPRequirements ·24. Typical Intel386 DX Microprocessor Clock Circuit RoutingPhysical Design and Debugging 27. Star Connectipn Thermal CharacteristicsDebugging Considerations Hardware Debugging FeaturesBus Interface Ffffo Simplest Diagnostic ProgramBuilding and Debugging a System Incrementally Other Simple Diagnostic Software EQU Debugging Hints 30. Object Code for Diagnostic Program Test Capabilities Page Internal Tests Chapter Test CapabilitiesAutomatic Self-Test TLR Translation Lookaside Buffer TestsBit Name Definition Test Capabilities BOARD..LEVEL Tests Page Local Bus Control PLD Descriptions Page IOPLD1 Functions Appendix a Local BUS Control PLD DescriptionsIOPLD2 Functions PLD Equations Figure A-1. IOPLD1Equations Figure A-1. IOPLD1 Equations Contd Figure A·1. IOPLD1 Equations Contd IIIIIIIIIInllllIIIIIIIIIIIIII Figure A-2. IOPLD2 Equations Contd Figure A-2. IOPLD2 Equations Contd Iowr Figure A-3. RESET/CLOCK PLD Equations Figure A-3. RESET/CLOCK PLDEquations Contd Figure A-3. RESET/CLOCK PLD Equations Contd Dram PLD Descriptions Page Dram PLDs Appendix B Dram PLD DescriptionsIUIIIIII11111111111111 DRAMP1 PLD Equations Contd Figure B-2. DRAMP1 PLD Equations Contd Figure B·2. DRAMP1 PLD Equations Contd DRAMP1 PLD Equations Contd DRAMP2 PLD Equations Figure B·3. DRAMP2 PLD Equations Contd Infel In+-I Figure B-3. DRAMP2 PLD Equations Contd Refresh Address Counter PLD Pin Description Refresh Address Counter PLDRefresh Address Counter PLD Equations In+-I RAS Page Page Page Page Page Page Page Page ~~~~e~~orp. Center Domestic Sales OfficesMTI Systems Sales Domestic DistributorsDOMESTIC, Distributors Contd Domestic Distributors Contd European Sales Offices International DISTRIBUTORS/REPRESENTATIVES International Sales OfficesCustomer Training Centers Domestic Service OfficesSystems Engineering Offices