Intel 386 manual In.teI

in.teI®			TABLE OF CONTENTS
			Figures
Figure			Title		Page
11-23	Closed Loop Signal Paths are Undesirable				11-27
11-24	Typical Intel386™		OX Microprocessor Clock Circuit		11-30
11-25	CLK2 Timing Diagram				11-30
11-26	Clock Routing		:		11-31
11-27	Star Connection			.	11-32
11-28	4-Byte Diagnostic Program				11-35
11-29	More Complex Diagnostic Program				11-38
11-30	Object Code for Diagnostic Program				11-40
12-1	Intel386™	OX Microprocessor Self-Test			12-2
12-2	TLB Test Registers				12-4
A-1	IOPLD1 Equations				A-3
A-2	IOPLD2 Equations				A-6
A-3	RESET/CLOCK PLD Equations				A-10
B-1	PLD Sampling Edges				B-1
B-2	DRAMP1 PLD Equations				B-2
B-3	DRAMP2 PLD Equations				B-7
B-4	Refresh Address Counter PLD Equations				B-13
			Tables
Table			Title		Page
1-1	Intel386™	Family System Components		,	1-4
3-1	Summary of Intel386™ OX Microprocessor Signal Pins				3-3
3-2	Bus Cycle Definitions				3-4
3-3	Possible Data Transfers on 32-Bit Bus				3-9
3-4	Misaligned Data Transfers on 32-Bit Bus				3-11
3-5	Generation of BHE#, BLE#, and Ai from Byte Enables				3-22
3-6	Byte Enables during BS16 Cycles				3-22
3-7	Output Pin States during RESET				3-36
4-1	Intel386™	OX Microprocessor Performance with Wait States and			4-2
	Pipelining			.
4-2	Performance versus Wait States and Operating Frequency				4-3
6-1	Common Logic Families*				6-3
6-2	DRAM Memory Performance				6-13
7-1	Cache Hit Rates			.	7-12
8-1	Data Lines for 8-Bit I/O Addresses				8-2
8-2	AO, Ai, and BHE# Truth Table				8-18
9-1	MULTIBUS I Timing Parameters				9-10
11-1	Voltage at End Points A and B				11-16
11-2	Comparison of Various Termination Techniques				11-22
11-3	Timing Specifications for CLK2				11-31
B-1	Refresh Address Counter PLD Pin Description				B-12

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