Intel 386 manual Non-Maskable Interrupt NMI

LOCAL BUS INTERFACE

depends on the type of interrupt; if the interrupt is maskable (INTR input active), the vector is supplied by the 8259A Interrupt Controller. If the interrupt is nonmaskable (NMI input active), location 2 in the IDT is used automatically.

The NMI request and the INTR request differ in that the Intel386 DX microprocessor can be programmed to ignore INTR requests (by clearing the interrupt flag of the Intel386 DX microprocessor). An NMI request always provokes a response from the Inte1386 DX microprocessor unless the Intel386 DX microprocessor is already servicing a previous NMI request. In addition, an INTR request causes the Intel386 DX micro- processor to perform two interrupt-acknowledge bus cycles to fetch the service-routine vector. These bus cycles are not required for an NMI request, because the vector loca- tion for an NMI request is fixed.

Under the following two conditions a service routine will not be interrupted by an incoming interrupt:

•The incoming interrupt is an INTR request, and the Intel386 DX microprocessor is programmed to ignore maskable interrupts. (The Intel386 DX microprocessor is automatically programmed to ignore maskable interrupts when it receives any inter- rupt request. This condition may be changed by the interrupt service routine.) In this case, the INTR request will be serviced only if it is still active when maskable inter- rupts are reenabled.

•The incoming interrupt is an NMI, and the Inte1386 DX microprocessor is servicing a previous NMI. In this case, the NMI is saved automatically to be processed after the IRET instruction in the NMI service routine has been executed. Only one NMI can be saved; any others that occur while the Intel386 DX microprocessor is servicing a previous NMI will not be recognized.

If neither of the above conditions is true, and an interrupt occurs while the Intel386 DX microprocessor is servicing a previous interrupt, the new interrupt is processed and ser- viced immediately. The Intel386 DX microprocessor then continues with the previous service routine. The last interrupt processed is the first one serviced.

If an NMI request and an INTR request arrive at the Inte1386 DX microprocessor simultaneously, the NMI request is processed first. Multiple hardware interrupts arriving at the 8259A are processed according to their priority and are sent to the Intel386 DX microprocessor INTR input one ,at a time.

3.4.1 Non-Maskable Interrupt (NMI)

The NMI input of the Intel386 DX microprocessor generally signals a catastrophic event, such as an imminent power loss, a memory error, or a bus parity error. This input is edge-triggered (on a low-to-high transition) and asynchronous. A valid signal is low for eight CLK2 periods before the transition and high eight CLK2 periods after the transi- tion. The NMI signal can be asynchronous to CLK2.

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