Intel 386 manual Figures

TABLE OF CONTENTS

Figures

Figure				Title			Page
7-15	Two-Way Set Associative Cache without Data Buffers						7-21
7-16	Two-Way Set Associative Cache with Data Buffers						7-22
8-1	32-Bit to 8-Bit Bus Conversion					.	8-3
8-2	Linear Chip Selects					.	8-5
8-3	Basic I/O Interface Block Diagram			, ..................:			8-6
8-4	I/O Controller Schematic					.	8-7
8-5	Basic I/O Timing Diagram		.............................................................................			.	8-10
8-6	8274 Interface		;			.	8-13
8-7	Single 8259A Interface					.	8-14
8-8	80286-Compatible Interface					.	8-17
8-9'	AO, A1, and BHE# Logic					.	8-19
8-10	SO#/S1 # Generator Logic					.	8-20
8-11	Wait-State Generator Logic					.	8-20
8-12	82288 and 82289 Connections					.	8-21
8-13	Intel386™	DX Microprocessor/82380 Interface				..............................................	8-22
8-14	LAN Station					.	8-23
8-15	Decoupled Dual-Port Memory Interface					.	8-24
8-16	Coupled Dual-Port Memory Interface					.	8-25
8-17	Shared Bus Interface					.	8-26
9-1	Intel386™	DX Microprocessor/MULTIBUS I Interface					9-3
9-2	MULTIBUS I Address Latches and Data Transceivers						9-4
9-3	Wait-State Generator Logic					.	9-6
9-4	MULTIBUS Arbiter and Bus Controller					.	9-7
9-5	MULTIBUS I Read Cycle Timing					'	9-8
9-6	MULTIBUS I Write Cycle Timing					.	9-9
9-7	Bus Priority Resolution					.	9-12 '
9-8	Operating Mode Configurations					,	9-13
9-9	Bus-Select Logic for Interrupt Acknowledge				........................	;	9-16
9-10	Byte-Swapping Logic					.	9-17
9-11	Bus-Timeout Protection Circuit					.	9-18
9-12	iLBXTM Signal Generation					.	9-19
10-1	iPSB Bus Cycle Timing			,			10-3
10-2	iPSB Bus Interface					~	10-4
11-1	Reduction in Impedance					.	11-4
11-2	Typical Power and Ground Trace Layout for Double-Layer Boards						11-5
11-3	Orthogonal Arrangement					.	11-6
11-4	. Circuit without Decoupling		....................................................................			,	11-7
11-5	Decoupling with Surface Mount Capacitors				...................................................		11-8
11-6	Decoupling with Leaded Capacitors				;...	,	11-8
11-7	Micro Strip Lines					.	11-10
11-8	Strip Lines	......................................................................................................				.	11-11
11-9	Overshoot and Undershoot Effects			...............................................................		.	11-12
11-10	Loaded Transmission Line		...............................			,	11-13
11-11	Lattice Diagram			,			11-15
11-12	Latt.ice Diag~am.Example			~		.	11-16
11-13	Senes Termination					.	11-18
11-14	Parallel Termination			'	;	:	11-18
11-15	Thevenins Equivalent Circuit					.	11-20
11-16	A.C. Termination					;	11-21
11-17	Active Termination					.	11-21
11-18	Impedance Mismatch Example					.	11-23
11-19	Use of Series Termination to Avoid Impedance Mismatch						11-23
11-20	Daisy Chaining					.	11-24
11-21	Avoiding 90-Degree Angles					.	11-24
11-22	Typical Layout '					.	11-26

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