Intel 386 - page 19

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TABLE OF CONTENTS
Figures
Title
Two-Way Set Associative Cache without Data Buffers ................................. .
Two-Way Set Associative Cache with Data Buffers ...................................... .
32-Bit to 8-Bit Bus Conversion ...................................................................... .
Linear Chip Selects ....................................................................................... .
Basic I/O Interface Block Diagram , .................. : ............................................ .
I/O Controller Schematic ............................................................................... .
Basic I/O Timing Diagram ............................................................................. .
8274
Interface ................. ; .............................................................................. .
Single 8259A Interface .................................................................................. .
80286-Compatible
Interface .......................................................................... .
AO, A1, and BHE# Logic ............................................................................... .
SO#/S1 # Generator Logic ............................................................................. .
Wait-State Generator Logic ........................................................................... .
82288
and 82289 Connections ..................................................................... .
Intel386™ DX Microprocessor/82380 Interface ............................................. .
LAN Station .................................................................................................... .
Decoupled Dual-Port Memory Interface ........................................................ .
Coupled Dual-Port Memory Interface ............................................................ .
Shared Bus Interface ..................................................................................... .
Intel386™ DX Microprocessor/MUL TIBUS I Interface ................................... .
MUL TIBUS I Address Latches and Data Transceivers ................................. .
Wait-State Generator Logic ........................................................................... .
MUL TIBUS Arbiter and Bus Controller .......................................................... .
MUL TIBUS I Read Cycle Timing ........................... ' ........................................ .
MULTIBUS I Write Cycle Timing ................................................................... .
Bus Priority Resolution .................................................................................. .
Operating Mode Configurations .......................................... , ......................... .
Bus-Select Logic for Interrupt Acknowledge ........................ ; ........................ .
Byte-Swapping Logic ..................................................................................... .
Bus-Timeout Protection Circuit ...................................................................... .
iLBXTM Signal Generation ................................................................................ .
iPSB Bus Cycle Timing ................ , ................................................................ .
iPSB Bus Interface ............................................................ ~ ............................. .
Reduction in Impedance ................................................................................ .
Typical Power and Ground Trace Layout for Double-Layer Boards ............ .
Orthogonal Arrangement ............................................................................... .
.
Circuit without Decoupling .................................................................... , ....... .
Decoupling with Surface Mount Capacitors .................................................. .
Decoupling with Leaded Capacitors .......... ; ... , .............................................. .
Micro Strip Lines ............................................................................................ .
Strip Lines ...................................................................................................... .
Overshoot and Undershoot Effects ............................................................... .
Loaded Transmission Line ............................... , ............................................. .
Lattice Diagram .............................. , ............................................................... .
Latt.ice Diag~am.Example .......................... ~ .................................................... .
Senes Termination ......................................................................................... .
Parallel Termination ....................... ' ............... ; ......................................... : ...... .
Thevenins Equivalent Circuit ......................................................................... .
A.C. Termination ............................................................................. ; .............. .
Active Termination ......................................................................................... .
Impedance Mismatch Example ..................................................................... .
Use of Series Termination to Avoid Impedance Mismatch .......................... .
Daisy Chaining ................................................................................................ .
Avoiding 90-Degree Angles ........................................................................... .
Typical Layout ' ................................................................................................ .
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