Intel 386 manual Address Decoder, Wait-State Generator

MULTIBUS I AND Intel386 DX MICROPROCESSOR

9.2.2 Address Decoder

A MULTIBUS I system typically has both shared and local memory. I/O devices can also be located either on MULTIBUS lora local bus. Therefore, the address space of the Inte1386 DX microprocessor must be allocated between MULTIBUS I and the local bus, and address decoding logic must be used to select one bus or the other.

The following two signals are needed for MULTIBUS I selection:

•Bus Size 16 (BS16#) must be returned active to the Intel386 DX microprocessor to ensure a 16-bit bus cycle. Additional terms for other devices requiring a 16-bit bus can be added to the BS16# PLD equation.

•MULTIBUS Enable (MBEN) selects the 82288 Bus Controller and the 82289 Bus Arbiter on the MULTIBUS I interface. Other outputs of the decoder PLD are pro- grammed to select memory and I/O devices on the local bus.

The decoding of addresses to select either the local bus or the MULTIBUS I is straight forward. In the following example, the system uses the first 64 megabytes of the Intel386 DX microprocessor memory address space, requiring 26 address lines. The MULTIBUS I memory is allocated to the addresses from FOOOOOH to F3FFFFH. The same PLD equation generates the two PLD outputs BS16# and MBEN:

/A25 * /A24 * A23 * A22 * A2l * A20 * /A19 * /A18

I/O resources residing on MULTIBUS I can be memory-mapped into the memory space of the Intel386 DX microprocessor or I/O-mapped into the I/O address space indepen- dent of the physical location of the devices on MULTIBUS I. The addresses of memory- mapped I/O devices must be decoded to generate I/O read or I/O write commands for memory references that fall within the I/O-mapped regions of the memory space. This technique is discussed in Chapter 8 along with the tradeoffs between memory-mapped I/O and I/O-mapped I/O.

9.2.3 Wait-State Generator

The wait-state generator controls the READY# input of the Inte1386 DX microproces- sor. For local bus cycles, the wait-state generator produces signal outputs that corre- spond to each wait state of the Inte1386 DX microprocessor bus cycle, and the PLD READY# output uses these signals to set READY# active after the required number of wait states. Two of the wait-state signals, WSI and WS2, are also used to generate SO# and Sl#.

READY# generation for MULTIBUS I cycles is linked to the Transfer Acknowledge (XACK#) signal, which is returned active by the accessed device on MULTIBUS I when the MULTIBUS I cycle is complete. For a system containing a MULTIBUS I interface as well as a local bus, XACK# must be incorporated into the wait-state generator to produce the READY# signal. The necessary logic is shown in Figure 9-3.

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