Intel 386 manual Power and Ground Planes

PHYSICAL DESIGN AND DEBUGGING

The worst-case power dissipation of any VLSI device is estimated in the following manner:

1.To estimate typical power dissipation for each circuit element: PG : Typical power dissipation for internal logic gates (mW) PI/a: Typical power dissipation for I/O buffers (mW)

2.To estimate total typical power dissipation:

PT = P G + PliO (mW) ... (1)

where PT is the total typical power dissipation (mW)

3. To estimate the worst case power dissipation:

Pd = PT X Cv (mW) ... (2)

where Pd is the worst case power dissipation (mW) and Cv is a multiplier that is dependent upon power supply voltage.

lnternallogic power dissipation varies with operating frequency and to some extent with wait-states and software. It is directly proportional to the supply voltage. Process varia- tions in manufacturing also affect the internal logic power dissipation, although to a lesser extent than with the NMOS processes.

The I/O buffer power dissipation, which accounts for roughly 10 to 25 percent of the overall power dissipation, varies with the frequency and the supply voltage. It is also affected by the capacitive bus load. The capacitive bus loadings for all output pins is specified in the Intel386 DX processor data sheet. The Inte1386 DX processor's output valid delays will increase if these loadings are exceeded. The addressing pattern of the software can affect I/O buffer power dissipation by changing the effective frequency at the address pins. The frequency variations at the data pins tends to be smaller; thus, a varying data pattern should not cause a significant change in the total power dissipation.

To calculate the total power dissipated by the board, the following formulas can be used:

To calculate the maximum statistical power:

PtypiCall + PtypiCal2 + .... [ (PmaxI - PtyPicall)2 + (Pmax2 - PtyPical2)2 + .....

where Pt icall and PmaxI are the typical and maximum power dissipation of each of the integrate~circuits on the board. The Inte1386 DX processor should be placed closer to

fan or where the airflow is unrestricted.

11.2.1 Power and Ground Planes

Today's high-speed CMOS logic devices are susceptible to the ground noise and the problems that this noise creates in digital system design. This noise is a direct result of the fast switching speed and high drive capability of these devices, which are requisites in

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