85C220

CLOCK.

RESET

GENERATOR

CLK

RESET CLK2

INTIPOo7

#. AO 8259A

CS# ~ i ~

TO

lA- INTERRUPT

1'1

l

~

(Xl

.!.J

I J.

T

RESET ClK2

A05#

INTR

NA#

M/IO#

W/R#

D/C

READY#

i386'~ OX

CPU

U

f --

-

 

-

 

,...---

. -

-

 

-

Pf1RDY

READY

AS

7aA3 ,74F138

CLK2 IOPLD1=:J

CLK10RDY

NA

TRIOEN -

MilO

-

WIR

INTA

D/C

EPRD

A31

IOWA

TIMEDLY

lORD

BUSCVC

RECV

 

CLK2

IOPLD2

~

 

 

 

 

f-

CLK

WICNTO ~

 

 

ADS

WTeNT1

-

 

 

READY

WTCNT2

-

 

 

INTA

P20R8

-

 

 

 

 

 

EPRDY

 

-

 

 

IOWR

PIRECYC

-

 

 

lORD

BUSCYC

-

 

-

RECV

ALEJO

-

 

CS1WS

TIMEDLY

-

~

-

CS3WS

CSSWS -

TTT

-INT' "IOWR

-----.-IORO

UI ::>

<II

~

Q

0

t-

_ 10

----.. CHIP

----.. SELECT

.::::::

o

Z

-I m :0

)l!

Q

z

C)

A12-A20

BEO#

BE1#

8516#

ADDRESS BUS

ADDRESS BUS

.--.

..........

DT/R# OEN#

~ALE#

r 74F373

LATCHES A1-A15

. 2

..

I

UI

OE

::>

 

<II

27256A

;!

 

EPROM

«

 

Q

V

. 2

0

 

t-

 

Ii

00-015

DATA BUS

 

~

--

.. 74F245

TRANSCEIVER

V. 2

TO DATA BUS

11

j

TO

 

 

 

DATA BUS

Y

231732i6-4

Figure 8-4. I/O Controller Schematic

Page 159
Image 159
Intel 386 manual Ttt