LOCAL BUS INTERFACE
3.6.1 HOLD/HLDA Timing
To gain control of the local bus, the requesting bus master drives the Inte1386 DX microprocessor HOLD input active. This signal must be synchronous to the CLK2 input of the Inte1386 DX microprocessor. The Inte1386 DX microprocessor responds by com- pleting its current bus cycle (plus a second locked cycle or a second cycle required by BS16#). Then the Intel386 DX microprocessor sets all outputs but HLDA to the three- state OFF condition to effectively remove itself from the bus and drives HLDA active to signal the requesting bus master that it may take control of the bus.
The requesting bus master must maintain HOLD active until it no longer needs the bus. When HOLD goes low, the Inte1386 DX microprocessor drives HLDA low and begins a bus cycle (if one is pending).
For valid system operation, the requesting bus master must not take control of the bus before it receives the HLDA signal and must remove itself from the bus before
When the Inte1386 DX microprocessor receives an active HOLD input, it completes the current bus cycle before relinquishing control of the bus. Figure
During the HOLD state, the Inte1386 DX microprocessor can continue executing instructions in its Prefetch Queue. Program execution is delayed if a read cycle is needed while the Intel386 DX microprocessor is in the HOLD state. The Intel386 DX micro- processor can queue one write cycle internally, pending the return of bus access; if more than one write cycle is needed, program execution is delayed until HOLD is released and the Inte1386 DX microprocessor regains control of the bus.
HOLD has priority over most bus cycles, but HOLD is not recognized between two interrupt acknowledge cycles, between two repeated cycles of a BS16 cycle, or during locked cycles. For the Inte1386 DX microprocessor, HOLD is recognized between two cycles required for misaligned data transfers; for the 8086 and 80286 HOLD it is not recognized. This difference should be considered if critical misaligned data transfers are not locked.
HOLD is not recognized while RESET is active, but is recognized during the time between the
All inputs are ignored while the Inte1386 DX microprocessor is in the HOLD state, except for the following:
•HOLD is monitored to determine when the Inte1386 DX microprocessor may regain control of the bus.
•RESET takes precedence over the HOLD state. An active RESET input will reini- tialize the Intel386 DX microprocessor.
•One NMI request is recognized and latched. It is serviced after HOLD is released.
