Intel 386 manual CLK2 nIUrL1lrtn-rtn-rtn-rtn-rtn-rtfLrtn-n.rurL1l

LOCAL BUS INTERFACE

Each bus cycle is comprised of at least two bus states, Tl and T2. Each bus state in turn consists of two CLK2 cycles, which can be thought of as Phase 1 and Phase 2 of the bus state. Figure 3-2 shows bus states for some typical read and write cycles. During the first bus state (Tl), address and bus status pins go active. During the second bus state (T2), external logic and devices respond. If the READY# input of the Intel386 DX micropro- cessor is sampled low at the end of the second CLK cycle, the bus cycle terminates. If READY# is high when sampled, the bus cycle continues for an additional T2 state, called a wait state, and READY# is sampled again. Wait states are added until READY# is sampled low.

When no bus cycles are needed by the Intel386 DX microprocessor (no bus requests are pending, the Intel386 DX microprocessor remains in the idle bus state (Ti). The rela- tionship between Tl, T2, and Ti is shown in Figure 3-3.

IDLE I	CYCLE 1		I	CyCLE 2				CYCLE 3
	NON-PIPELINED			NON-PIPELINED				NON-PIPELINED
		(READ)		(WRITE)				(READ)
n	T1	T2	T1	T2	T2	TI	T1	T2	T2	n

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A2-A31. [ XX IX VALID 1 IX VALID 2xxxxx VALID 3 ~:xxx M/IO#.D/CH

W/R# [	XIXXXXIX			1/			,{XXX>"		~
ADS # [	f\.- r - ~I						\ - I
NA# [	IXXXXIXXX		XX	XX		~xxx	XXXIXXX	'<XXXXIXXXX
		32-BIT				32-BIT			32-BIT
		BusllZE				BUSiSIZE			BUStZE
8S16 # [	Xl>\X.X.Xl>\X.X.X y		'(XXXXXXXXY				XXXIXXX	xx	'<M2S.2!
READY# [	XIXXXxIXXXX XXX			AM XXJ		~	'(XXIXXX	XT	~ m
			END CYCLE 1			END CYCLE 2			END CYCLE 3
LOCK# [	XIXXXXIX	VALID 1		IX	VALID 2		IXXX IX	VALID 3	IXXXX
00- 031 [	- ----------~--~< OUT						)-------	----	--~---

Idle states are shown here for diagram variety only. Write cycles are not always followed by an idle state. An active cycle can immediately follow the write cycle.

231732i3-2

Figure 3·2. Inte1386'MOX CPU Bus States Timing Example

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