Intel 386 manual ~~~~----------~~

CACHE SUBSYSTEMS

8Kx8

8Kx8

8Kx8

				<t
CACHE				!;:
				C
SRAM				CIl	CALEN
(8Kx 8)		~~~~----------~~
		4x245		...J
		1	SIJL---I--''\~
	OATA .1U-L---'\IA
CSO#-			00-031	~		82385
CS3#	WEI					CACHE
					CT/R#	CONTROL

COEA#

CSO#-CS3#

4

231732;7-14

Figure 7-14. Direct Mapped Cache with Data Buffers

4Kx4

CACHE SRAM
BANK A	CALEN
(4Kx4)

82385

CACHE

CWEA# CONTROL

COEA#

CSO#-CS3#

CWEB#

COEB#

ADDRESS

CACHE SRAM

BANK B (4K,32)

DATAI¢========+~

00-031

231732;7-15

Figure 7-15. Two-Way Set Associative Cache without Data Buffers

7-21