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| PHYSICAL DESIGN AND DEBUGGING |
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| ·PAGE | 66,132 | |
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| EQUATES |
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00C8 |
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| LATCH | EQU | 0C8H |
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00AA |
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| GOOLSIGNAL | EQU | 0AAH |
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0055 |
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| BALSIGNAL | EQU | 055H |
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| CODE TO VERIFY ABILITY TO WRITE | |||
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| AND | READ RAM CORRECTLY | ||
0000 |
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| INITIAL_CODE | ASSUME | CS:INITIAL_CODE | |
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| SEGMENT |
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F000 |
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| ORG | 0F000H | |
F000 | BB | 0000 |
| TSLLOOP: | MOV | BX, | 0000H | |
F003 | 8E | DB |
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| MOV | DS, | BX |
F005 | C7 | 07 | 5473 |
| MOV | [BX1, 5473H | ||
F009 | C7 | 47 | 02 | 2961 |
| MOV | [BX1+2, 2961H | |
F00E | EB | 01 | 90 |
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| JMP | READ |
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F011 | 81 | 3F | 5473 | READ: | CMP | [BXl, 5473H | ||
F015 | 75 | 0D |
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| JNE | BADRAM | |
F017 | 81 | 7F | 02 | 2961 |
| CMP | [BX1+2, 2961H | |
F01C | 75 | 06 |
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| JNE | BAD RAM | |
F01E | B0 | AA |
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| MOV | AL, | GOOLSIGNAL |
F020 | E6 | C8 |
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| OUT | LATCH, AL | |
F022 | EB | DC |
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| JMP | TSLLOOP | |
F024 | B0 | 55 |
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| BADRAM: | MOV | AL, | BALSIGNAL |
F026 | E6 | C8 |
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| OUT | LATCH, AL | |
F028 | EB | D6 |
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| JMP | TSLLOOP | |
FFF0 |
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| ORG | 0FFF0H | |
FFF0 | E9 | F000 | R | START: | JMP | TSLLOOP | ||
FFF3 |
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| INITIAL_CODE | ENDS |
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| END |
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Warning | Severe |
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Errors |
| Errors |
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0 |
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Figure 11-30. Object Code for Diagnostic Program
cycle, waiting for the READY# signal to go active. The address at the address latch outputs and the states of the W/R#, D/C#, and M/IO# signals should be checked to narrow the investigation to a specific part of the READY# generation circuit. Then the circuit should be investigated with the logic analyzer.
Once the basic system is built and debugged, more software and further enhancements can be added to the system. The incremental approach described applies to these addi- tions. Systematic,
