MEMORY INTERFACING
EPROMs only for power-on initialization and runs programs entirely from SRAM or DRAM has only a power-on time increase over the 32-bit EPROM system; its main programs run at the same speed as the 32-bit system.
The Intel386 DX microprocessor BS16# input directs the Intel386 DX microprocessor to perform data transfers on only the lower 16 bits of the data bus. In systems in which 16-bit memories are used, the address decoder logic must generate the BS16# signal for 16-bit accesses. Since NA# cannot be asserted during a bus cycle in which BS16# is asserted (because the current address may be needed for additional cycles), the decoder logic should also guarantee that the NA# signal is not generated. When the Intel386 DX microprocessor samples BS16# active and NA# inactive, it automatically performs any extra bus cycles necessary to complete a transfer on a 16-bit bus. The Intel386 DX microprocessor response is determined by the size and alignment of the data to be transferred, as described in Chapter 3.
6.3 DYNAMIC RAM (DRAM) INTERFACE
This section presents a dynamic RAM (DRAM) memory subsystem design that is both cost-effective and fast. The design can be adapte!i for a wide variety of speed and system requirements to provide high throughput at minimum cost. The DRAM design in this section illustrates DRAM subsystem design concepts and analysis. This system would be suitable for use as the main memory of an 82385 cache system described in Chapter 7. Because the 82385 cache controller provides the majority of memory requests in zero wait states, the performance of the main memory is less critical.
6.3.1 Interleaved Memory
DRAMs provide relatively fast access times at a low cost per bit; therefore, large mem- ory systems can be created at low cost. However, DRAMs have the disadvantage that they require a brief idle time between accesses to precharge; if this idle time is not provided, the data in the DRAM can be lost. If back-to-back accesses to the same bank of DRAM chips are performed, the second access must be delayed by the precharge time. To determine if additional idle states will be needed, compare the DRAM cycle time to the cycle length of the Inte1386 DX microprocessor. To avoid this delay, memory should be arranged so that each subsequent memory access is most likely to be directed to a different bank. In this configuration, wait· time between accesses is not required because while one bank of DRAMs performs the current access, another bank pre- charges and will be ready to perform the next access immediately.
Most programs tend to make subsequent accesses to adjacent memory locations during code fetches, stack operations, and array accesses, for example. If DRAMs are inter- leaved (i.e., arranged in multiple banks so that adjacent addresses are 'in different banks), the DRAM precharge time can be avoided for most accesses. With two banks of DRAMs, one for even 32-bit doubleword addresses and one for odd doubleword addresses, all sequential 32-bit accesses can be completed without waiting for the DRAMs to precharge.
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