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Intel 386 manual

Models: 386

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Thermal Characteristics Lattice Diagram READY# Signal Timing Logic Delay Operating Mode Configurations Reset Simplest Diagnostic Program Resolution Power and Ground Planes Domestic Service Offices

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Intel 386 manual

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Contents

Page Infel Current HandbooksCanada Literature Order Form International Literature Order Form Name Company ~ Address City State ZIP CountryMicroprocessor Hardware Reference Manual Intel Corporation 1986 CG-072391 Intels Complete Support Solution Worldwide Customer SupportPage Preface Related PublicationsOrganization of this Manual Preface Page Table of Contents Chapter Performance Considerations Chapter Cache Subsystems Chapter Table of Contents Chapter Physical Design and Debugging Figures Figures In.teI System Overview Page Chapter System Overview MicroprocessorLntel386 OX Microprocessor System Block Diagram Micro Channel-Compatible Solution with 82311 Chip Set Coprocessors Integrated System PeripheralCache Controller Eisa Chip SET 8086/80286 Family Components LAN CoprocessorClock Generator Intel Programmable Logic Devices Internal Architecture Page Chapter Internal Architecture Instruction Decode Unit BUS Interface UnitCode Prefetch Unit =i m Paging Unit Execution UnitSegmentation Unit Local Bus Interface Page Chapter Local BUS Interface BUS Operations Summary of Intel386 OX Microprocessor Signal Pins Bus StatesClK2and ClK Relationship CLK2 nIUrL1lrtn-rtn-rtn-rtn-rtn-rtfLrtn-n.rurL1l Address Pipelining 3 32-Bit Data Bus Transfers and Operand AlignmentLocal BUS Interface Consecutive Bytes in Hardware Implementation Possible Data Transfers to 32-Bit Memory Misaligned Transfer Read Cycle Non-Pipelined Address Read Cycles Write Cycle Pipelined Address CycleNon-Pipelined Address Write Cycles ~~r-...............-r--+-----r-------r-.......~---f\j~~ Interrupt Acknowledge Cycle JUlrutrutrulrutrutrutillh.Ilrutruln.n Halt/Shutdown Cycle9 8516 Cycle 10 i6-Bit Byte Enables and Operand Alignment 13 compares the signals for 32-bit and 16-bit bus cycles13 -Bit and 16-Bit Bus Cycle Timing DIS-DO LOCALBU51NTERFACE BUS Timing READY# Signal Timing Clock Generation Clock TimingCrystal Oscillator Clock Generator 16.Clock GeneratorInterrupts 17. ADS# SynchronizerNon-Maskable Interrupt NMI Maskable Interrupt Intr Interrupt LatencyBUS Lock Locked Cycle ActivatorsEJj Locked Cycle TimingLOCK# Signal Duration HOLD/HLDA Hold AcknowledgeHOLD/HLDA Timing Hold Signal Latency Reset Reset TimingHold State Pin Conditions Intel386 OX Microprocessor Internal StatesRES# ~----------5S 5 mml Performance Considerations Page Chapter Performance Considerations Wait States and PipeliningWait States Performance versus Wait States and Operating Frequency Page Coprocessor Hardware Interface Page Chapter Coprocessor Hardware Interface Intel387 OX Math Coprocessor Interface Intel387 OX Math Coprocessor ConnectionsInteI386OX CPU System with Intel387MOX Math Coprocessor Intel387 OX Math Coprocessor Bus Cycles Intel387 OX Math Coprocessor Clock InputLocal BUS Activity with the Intel387 OX Math Coprocessor CLK2Software Recognition of the NPX 80287/lnte1387 OX Math Coprocessor RecognitionHardware Recognition of the NPX Software Routine to Reco.gnize the Coprocessor Coprocessor .HARDWARE Interface Memory Interfacing Page Basic Memory Interface Chapter Memory InterfacingMemory Speed Versus Performance and Cost Flb TTL DevicesPLD Devices Common Logic FamiliesMemory Interfacing =8= Address Latch Address DecoderData Transceiver Bus Control Logic~~Y Eprom Interface Nanosecond Eprom Timing Diagram 8 16-Bit Interface Dynamic RAM Dram Interface Interleaved MemoryDram Memory Performance Dram Memory PerformanceDram Controller 3.1 3-ClK Dram CONTROllERIIII~ DRAMP2 Memory Interfacing ClK Y Y \JY ~1\Dram Timing Analysis Logic Delay = 50 30 6 + + 3 + Avoiding Data BUS Contention Control Signal Timings Logic Paths Dram Design Variations Using TAP Delay Lines Refresh Cycles 5.2 BUR&T Refresh Initialization Cache Subsystems Page Chapter Cache Subsystems Cache Memory SystemBlock Fetch Introduction to CachesProgram Locality Cache Organizations Fully Associative CacheDirect Mapped Cache Direct Mapped Cache Organization Set Associative Cache Cache Subsystems Buffered Write-Through System Cache UpdatingWrite-Through System Write-Back System 3B6oOX CPU -uCache Coherency Bus WatchingEfficiency and Performance Hardware TransparencyNon-Cacheable Memory Example Design Cache and DMACache Example Example Cache Memory Organization Example of Cache Memory Organization Bus Structure with 2 82385/lnte1386 OX Microprocessor Interface 11. Intel386 OX Microprocessor/82385 System Bus Structure12. Intel386 OX Microprocessor/82385 Interface 2.3 82385 System Configuration Inputs 3 82385 Cache Organiza~ion 13.Direct Mapped Cache without Data Buffers~~~~----------~~ 74AS~~ x~- ~ CWEB# Write Cycles System Interface Special Design NotesCache Subsystems Page Interfacing Page 8-BIT, 16-BIT, and 32-BIT I/O Interfaces Chapters InterfacingI/O Mapping Versus Memory Mapping Address Decoding 2 8-Bit I/OInterfacing 3 16-Bit I/O 4 32-Bit I/OLinear Chip Selects Basic I/O InterfaceAddress Latch ~ #1 TTT 111tJI Timing Analysis for I/O Operations \.LI,1l Xcvr. prop Min Basic I/O Examples 1 8274 Serial Controller2 82380 Programmable Interrupt Controller #- IRS 3 8259A Interrupt ControllerCascaded Interrupt Controllers 80286-COMPATIBLE BUS Cycles 1 AO/A1 Generator 2 SO#/S1 # Generator O21 Bus Controller and Bus Arbiter DIC. --t-~=r-\---+---.J5 82380 Integrated System Peripheral 6 82586 LAN Coprocessor·13. Intel386 OX Microprocessor/82380 Interface 14. LAN Station Dedicated CPU Decou Pled DUAL-PORT Memory Coupled DUAL-PORT Memory 17. Shared Bus Interface MULTIBUSland9 Intel386 ox Microprocessor Page Chapter Multi BUS I and Intel386 DX MicroprocessorMultibus I Interface Example Address Latches and Data TransceiversBUS ·2. Multibus I Address Latches and Data Transceivers Wait-State Generator Wait-State Generator Logic BUSY# Ex L-lLS Pcb Timing Analysis of Multibus I Interface Priority Resolution 2 82289 Operating ModesBus Priority Resolution Operating Mode Configurations Interrupt-Acknowledge on Multibus Multibus I Locked CyclesOther Multibus I Design Considerations Byte Swapping during Multibus I Byte Transfers »-+-J¢l~~~ Bus Timeout Function for Multibus I Accesses ALE~Multibus I Power Failure Handling ~----I~ DUAL-PORT RAM with Multibus Avoiding Deadlock with Dual-Port RAMMUL Tibus II Intel386 OX Microprocessor Page Multibus II Standard Parallel System BUS iPSBShows how the timing of these cycles overlap IPSB Bus Cycle Timing IPSe Interface IPSB Bus Interface10-5 MIC Signals Local BUS Extension iLBX Serial System BUS iSSBPage Physical Design Page General Design Guidelines Power Dissipation and DistributionChapter Physical Design and Debugging Power and Ground Planes EMI, which will be discussed in Section Roo Decoupling CapacitorsGNO Sx/1 Physical Design and Debugging ~O~ High Frequency Design ConsiderationsTransmission Line Effects +1~ +~---------Dielectric ~~---T-ime---~--~~~= Impedance Mismatch10. Loaded Transmission Line + TI Vst-tpd2L-xHt-tpd 2L-x + TITs Vst-tpd2L+x Ht-tpd2L+x 11. Lattice Diagram ~.-----..-.r Tpo 3.02 Need for Termination NVv Thevenins Equivalent Termination ·15. Thevenins Equivalent Circuit 1111 Impedance Matching Example Daisy Chaining Interference 20. Daisy ChainingElectromagnetic Interference CROSS-TALK 22. Typical Layout 23. Closed Loop Signal Paths are Undesirable Propagation Delay Requirements LATCH-UPClock Considerations Routing ·24. Typical Intel386 DX Microprocessor Clock CircuitPhysical Design and Debugging Thermal Characteristics 27. Star ConnectipnHardware Debugging Features Debugging ConsiderationsBus Interface Simplest Diagnostic Program FfffoBuilding and Debugging a System Incrementally Other Simple Diagnostic Software EQU Debugging Hints 30. Object Code for Diagnostic Program Test Capabilities Page Automatic Self-Test Chapter Test CapabilitiesInternal Tests Translation Lookaside Buffer Tests TLRBit Name Definition Test Capabilities BOARD..LEVEL Tests Page Local Bus Control PLD Descriptions Page IOPLD2 Functions Appendix a Local BUS Control PLD DescriptionsIOPLD1 Functions PLD Equations Figure A-1. IOPLD1Equations Figure A-1. IOPLD1 Equations Contd Figure A·1. IOPLD1 Equations Contd IIIIIIIIIInllllIIIIIIIIIIIIII Figure A-2. IOPLD2 Equations Contd Figure A-2. IOPLD2 Equations Contd Iowr Figure A-3. RESET/CLOCK PLD Equations Figure A-3. RESET/CLOCK PLDEquations Contd Figure A-3. RESET/CLOCK PLD Equations Contd Dram PLD Descriptions Page Appendix B Dram PLD Descriptions Dram PLDsIUIIIIII11111111111111 DRAMP1 PLD Equations Contd Figure B-2. DRAMP1 PLD Equations Contd Figure B·2. DRAMP1 PLD Equations Contd DRAMP1 PLD Equations Contd DRAMP2 PLD Equations Figure B·3. DRAMP2 PLD Equations Contd Infel In+-I Figure B-3. DRAMP2 PLD Equations Contd Refresh Address Counter PLD Refresh Address Counter PLD Pin DescriptionRefresh Address Counter PLD Equations In+-I RAS Page Page Page Page Page Page Page Page Domestic Sales Offices ~~~~e~~orp. CenterDomestic Distributors MTI Systems SalesDOMESTIC, Distributors Contd Domestic Distributors Contd European Sales Offices International Sales Offices International DISTRIBUTORS/REPRESENTATIVESSystems Engineering Offices Domestic Service OfficesCustomer Training Centers