SYSTEM OVERVIEW
The
82385
I Cache Controller
is
a high performance peripheral designed specifically for
. the Intel386
DX
microprocessor. The
82385
allows the Intel386 DX microprocessor to
reach its full performance potential
by
offering the following features:
Supports a 32-kbyte cache memory organized
as
either
2-way
set associative
or
direct
mapped.
Integrated cache directory and management logic.
Utilizes posted writes for zero wait states on write cycles.
Guarantees cache coherency
by
bus watching.
Supports non-cache able accesses.
Presents an Inte1386 DX microprocessor interface to system resources.
Dhrystone benchmark shows an average hit rate of 95%.
1.5 EISA CHIP SET
EISA extends the 32-bit transfer capability of the Intel386 DX microprocessor to the I/O
expansion bus. The
82350
chip set
is
a highly integrated solution in a 5-piece chip set
using 3 components:
82358
EISA Bus Controller
82357
Integrated System Peripheral
82352 EISA Bus Buffer
(3
used)
The
82355
Bus Master Interface Controller (BMIC)
is
provided for add-in board sup-
porL The BMIC provides all of the necessary control signals, address lines and data lines
for an EISA bus master to interface to the EISA bus.
The EISA specification and the
82350
chip set are both designed to
be
100% backward
compatible to the ISA (Industry Standard Architecture) AT-bus. Therefore, software
and add-in boards designed for the ISA bus
may
be used in higher performance EISA
systems.
This high performance, high integration
82350
EISA solution
is
designed to be used with
the Intel486
DX
and Intel386 SX microprocessors as.well
as
the Intel386 DX micropro-
cessor (up to and including
33
MHz).
1.6 MCA CHIP SET
The
82311
chip set consists of standard peripheral components for implementing an
IBM PS/2 compatible motherboard which supports the Micro Channel Architecture.
Included in the Micro Channel compatible chip set are seven highly integrated VLSI
peripherals including:
e'
82303
Local I/O Support Chip
82304 Local I/O Support Chip
82307
DMNCACP
Controller
1-6