Intel 386 manual Chapter Performance Considerations, Wait States and Pipelining

CHAPTER 4

PERFORMANCE CONSIDERATIONS

System performance measures how fast a microprocessing system performs a given task or set of instructions. Through increased processing speed and data throughput, a Inte1386 DX microprocessor operating at the heart of a system can improve overall performance immensely. The design of supporting logic and devices for efficient inter- action with the Intel386 DX microprocessor is also important in optimizing system performance.

This chapter describes consideratiQns for achieving high performance in Intel386 DX microprocessor-based systems. A variety of examples illustrate the potential perfor- mance levels for a number of applications. Two general methods can be used to match .' the speed of the Intel386 DX CPU to external devices: bus cycle timing or caches. Bus cycle timing includes wait states and pipelining option. Chapter 7· discusses caches.

4.1 WAIT STATES AND PIPELINING

Because a system may include devices·whose response is slow relative to the Inte1386 DX microprocessor bus cycle, the overall system performance is often less than the potential performance of the Inte1386 DX microprocessor. Two techniques for accommodating slow devices are wait states and address pipelining. The designer must consider how to use one or both of these techniques to minimize the impact of device performance on system performance.

The impact of memory device speed on performance is generally much greater than that of I/O device speed because most programs require more memory accesses than I/O accesses. Therefore, the following discussion focuses on memory performance.

Wait states are extra CLK cycles added to the Inte1386 DX microprocessor bus cycle. External logic generates wait states by delaying the READY# input to the Intel386 DX microprocessor. For an Intel386 DX microprocessor operating at 33 MHz, one wait state adds 30 nanoseconds to the time available for the memory to respond. Each wait state increases the bus cycle time by 50 percent of the zero wait-state cycle time; however, overall system' performance does not vary in direct proportion to the bus cycle increase. The second column of Table 4-1shows the performance impact (based on an example simulation) for memory accesses requiring different numbers of wait states; one wait state results in an overall performance decrease of 19 percent.

Unlike a wait state, address pipelining increases the time that a memory has to respond by one CLK cycle without lengthening the bus cycle. This extra CLK cycle eliminates the output qelay of the Inte1386 DX microprocessor address and status outputs. Address pipelining overlaps the address and status outputs of the next bus cycle with the end of the current bus cycle, lengthening the address access time by one or more CLK cycles from the, point of view of the accessed memory device. An access that requires two wait

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