Intel 386 manual Bit and 16-Bit Bus Cycle Timing

LOCAL BUS INTERFACE

IDLE CVCLE1

INON·PIPELINED (WRITE)

TI T1 T2

CLK2

CLK

BEO#-BE3#,

A2-A31,

MIIO#, D/C#

WIR#

~JVq

AOS#

BS16#

~£.lllp~

	A TRANSFER REQUIRING TWO
	CYCLES ON 16·BITDATA BUS				I
IDLE	CVCLE1A			CVCLE1
	NON·PIPELINEO		NON·PIPELINED
		WRITE)		(WRITE
	PART TWO		PART ONE
TI	T1	T2	T1	T2

CLK2

CLK

BEO#, BE1#

CJpL.l£lUt"'----I-~

BE2#, BE3#, nb~-,j,V"--i---i---i--""i

A2-A31 ,

MIIO#, OIC# .ajC:J.~I£lI'\.--+---+---+---f

AOS#

B516#

00-015

231732i3-13

Figure 3-13. 32-Bit and 16-Bit Bus Cycle Timing

3-20