MEMORY INTERFACING
along with the address. Therefore, the number of address latches needed is determined by the location of the address decoder as well as the number of address bits and chip- select signals required by the interface. Chip-select signals can be routed to the bus control logic to set the correct number of wait states for the accessed device.
The decoder consists of two one-of-four decoders, one for memory address decoding and one for I/O address decoding. In general, the number of decoders needed depends on the memory mapping complexity. The 85C508 EPLD performs both address decoding and latching functions in a single device. In this basic example, the A31 output is suffi- cient to determine which memory device is to be selected.
6.2.5 Data Transceiver
Standard 8-bit transceivers (74x245, in this example) provide isolation and additional drive capability for the Intel386 DX microprocessor data bus. Transceivers are necessary to prevent the contention on the data bus that occurs if some devices are slow to remove read data from the data bus after a read cycle. If a write cycle follows a read cycle, the Intel386 DX microprocessor may drive the data bus before a slow device has removed its outputs from the bus, potentially causing reliability problems. Transceivers can be omit- ted only if the data float time of the device is short enough and the load on the Intel386 DX microprocessor data pins meets device specifications.
A bus interface must include enough transceivers to accommodate the device with the most inputs and outputs on the data bus. Normally, 32-bit-wide memories, which require four 8-bit transceivers, are used in Inte1386 DX microprocessor systems.
The 74x245 transceiver is controlled through two input signals:
•Data Transmit/Receive (DT/R#) - When high, this input enables the transceiver for a write cycle. When low, it enables the transceiver for a read cycle. This signal is just a latched version of the Inte1386 DX microprocessor W/R# output.
•Data Enable (DEN#)- When low, this input enables the transceiver outputs. This
signal is generated by the bus control logic. | . |
6.2.6 Bus Control Logic
Bus control logic is shown in Figure 6-4. The bus controller is implemented in two PLDs. One PLD (IOPLD1) follows the Intel386 DX microprocessor bus cycles and generates the overall bus cycle timing. The second PLD (IOPLD2) generates most of the bus control signals. The equations for these PLDs are listed in Appendix A of this manual.
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