MULTIBUS II AND Intel386 OX MICROPROCESSOR
The bus agent that receives a transfer cycle from the bus owner must have its BAC enabled by an active SELECT input. Errors detected by the replying agent are encoded by its MIC on the AGERR2-AGERRO inputs to its BAC so that the BAC can drive the SC7#-SC5# lines accordingly. If an error occurs, the requesting agent notifies the Intel386 DX microprocessor through the EINT signal.
The register interface signals control register operations between the Inte1386· DX microprocessor and the BAC. Three 5-bit registers (Arbitration ID, Slot ID, and Error Port) are addressed through RSELl and RSELO. Data is transferred on RI04-RIOO; the direction of transfer is indicated by RRW.
10.2.1.2 MIC SIGNALS
The MIC coordinates interrupt handling for a bus agent on the iPSB bus. Interrupts are implemented as virtual interrupts in the message space. To send an interrupt message, the Inte1386 DX microprocessor writes four bytes to the MIC to indicate the source, destination, and type of message. The MIC then coordinates the message transfer. The MIC of the receiving bus agent reads the 4-byte message and stores it in a 4-deep message queue to be read by the Intel386 DX microprocessor.
The MIC signals are divided into three groups:
•iPSB interface
•Local bus interface
•BAC interface
The iPSB interface consists of the multiplexed address/data bus (AD31#-ADO#). Although the MIC gains access to the iPSB bus through the BAC, the MIC drives the address/data bus directly. As a requesting agent, the MIC drives the address and data at the appropriate times. As a receiving agent, the MIC monitors the address/data bus for its address. When it recognizes its address, the MIC selects its BAC to perform the required handshake and read the message into the message queue. Then, the MIC inter- rupts the Intel386 DX microprocessor to indicate that the message is pending in the queue. The Intel386 DX microprocessor reads the message and services the interrupt accordingly.
The local bus interface consists of seven register/ports, addressed through A2-AO, through which the MIC and the Intel386 DX microprocessor communicate. Data is transferred over D7-DO, and WR# and RD# determine the direction of transfer. Other signals include the MIC Chip Select (CS#), a WAIT# signal for adding wait states to the Inte1386 DX microprocessor cycle, and a Message Interrupt (MINT) to signal an interrupt condition to the Inte1386 DX microprocessor.
The BAC interface includes REQUESTB, ·READYB, SELECTB, and GRANTB. These signals have already been described with the other BAC signals.
While the BAC and the MIC together provide the backbone for an iPSB interface, other logic provides buffering and control to round out the interface. An 8751 Microcontroller coordinates Intel386 DX microprocessor access to the interconnect space. An address
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