Intel 386 manual Multibus I Interface Example, Address Latches and Data Transceivers

MULTIBUS I AND Intel386 DX MICROPROCESSOR

One method of constructing an interface between the Intel386 DX microprocessor and the MULTIBUS I is to generate all MULTIBUS I signals using only TTL and PLD devices. A simpler method is to use the 80286-compatible interface described in Chapter 8. The latter option is described in the MULTIBUS I interface example in this chapter.

9.2 MULTIBUS I INTERFACE EXAMPLE

The MULTIBUS I interface presented in the following example consists of the 80286- compatible, 82289 Bus Arbiter and 82288 Bus Controller. The 82289, along with the bus arbiters of other processing subsystems, coordinates control of the MULTIBUS I; the 82288 provides the control signals to perform MULTIBUS I accesses. Communication between the Intel386 DX microprocessor and these devices is accomplished through PLDs that are programmed to perform all necessary signal translation and generation. Latching and buffering of the data and address buses is performed by TTL logic.

Figure 9-1 shows a block diagram of the interface, which consists of the following parts:

•AO/Al generator - Generates the lower address bits from Inte1386 DX microproces- sor BEO#-BE3# outputs

•Address decoder - Determines whether the bus cycle requires a MULTIBUS I access

•MULTIBUS I address latches-Connect directly to Intel386 DX microprocessor address pins A23-A2 and the outputs of the AO/Al generator

•MULTIBUS I data latch/transceivers - Connect directly to Intel386 DX microproces- sor data pins DIS-DO

•SO#/SI# generator-Translates Intel386 DX microprocessor outputs into the SO# and SI# signals

•Wait-state generator-Controls the length of the Inte1386 DX microprocessor bus cycle through the READY# signal

•82288 Bus Controller-Generates the MULTIBUS I command signals

•82289 Bus Arbiter - Arbitrates contention for bus control between the Intel386 DX microprocessor and other MULTIBUS I masters

These elements of the 80286-compatible interface are described in detail in Chapter 8. The block diagram in Figure 9-1 does not include the Intel386 DX microprocessor local bus interface and local resources. In a complete system, some logic (for example, the address decoder) is common to both MULTIBUS I and local bus interfaces. The follow- ing discussion includes only the logic necessary for the MULTIBUS I interface.

9.2.1 Address Latches and Data Transceivers

MULTIBUS I allows up to 24 address lines and 16 data lines. In this example, the MULTIBUS addresses are located in a 2S6-kilobyte range between FOOOOOH and F3FFFFH, so that all 24 address lines are used. The 16 data lines correspond to the lower half of the Inte1386 DX microprocessor data bus.

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