Motorola DSP56301 manuals

372 pages4.88 Mb

2How to reach us:
1-303-675-2140 1-800-441-2447
5Contents
- Chapter 1 Overview
- Chapter 2 Signals/Connections
- 6Chapter 3 Memory Configuration
- Chapter 4 Core Configuration
- 7Chapter 5 Programming the Peripherals
- Chapter 6 Host Interface (HI32)
- 8Chapter 7 Enhanced Synchronous Serial Interface (ESSI)
- 9Chapter 8 Serial Communication Interface (SCI)
- 10Chapter 9 Triple Timer Module
- Chapter A Bootstrap Program Chapter B Programming Reference
- Index
11Figures
15Tables
17Chapter 1 Overview
- 1.1 Manual Organization
- 181.2 Manual Conventions
- 201.3 DSP56300 Core Features
- 221.4 DSP56300 Core Functional Blocks
  - 1.4.1 Data ALU
  - 231.4.2 Address Generation Unit (AGU)
  - 241.4.3 Program Control Unit (PCU)
  - 251.4.4 PLL and Clock Oscillator
  - 1.4.5 JTAG TAP and OnCE Module
    - .
  - 1.4.6 On-Chip Memory
- 261.5 Internal Buses
  - DMA
  - The block diagram in Figure 1-1 illustrates these buses among other components.
    - Expansion Area
    - Figure 1-1. DSP56301 Block Diagram
- 271.6 DMA
  - The DMA block has the following features:
    - Memory Expansion Area
    - Peripheral
- 281.7 Peripherals
  - 1.7.1 General-Purpose Input/Output (GPIO ) signals
  - 1.7.2 Host I nte rface (HI32)
  - 1.7.3 E nhance Synchronous Serial Interface (ESSI)
  - 291.7.4 Serial Communications Interface (SCI)
  - 1.7.5 Triple Timer Module
- 301.8 Related Documents and Web Sites
31Chapter 2 Signals/Connections
- Table 2-1. DSP56301 Functional Signal Groupings
- 32Figure 2-1. Signals Identified by Functional Group
  - 2-2 DSP56301 Users Manual
  - DSP56301
    - 3
    - 24
    - 24
    - 52
  - Port A
    - See Figure 2-2 for a listing of the Host Interface/Port B Signals
- 33Figure 2-2. Host Interface/Port B Detail Signal Diagram
  - Signals/Connections 2-3
  - DSP563 01
  - (HI32)
  - Host Interface
  - Port B Signa ls
  - PCI Bus Universal Bus Port B GPIO Host Port (HP) Reference
  - Power
  - 2-4 DSP56301 Users Manual
- 342.1 Power
- 2.2 Ground
  - Table 2-2. Power Inputs
  - Table 2-3. Ground Signals
    - Clock
- 352.3 Clock
- 2.4 PLL
  - Table 2-4. Clock Signals
  - Table 2-5. Phase-Lock Loop Signals
    - 2-6 DSP56301 Users Manual
- 362.5 External Memory Expansion Port (Port A)
  - 2.5.3 External Bus Control
    - RD, WR, BB, CAS, BCLK, BCLK.
  - 2.5.1 E xternal Address Bus
  - 2.5.2 External Data Bus
    - Table 2-6. External Address Bus Signals
    - Table 2-7. External Data Bus Signals
    - Table 2-8. External Bus Control Signals
    - 37Table 2-8. External Bus Control Signals (Continued)
      - 2-8 DSP56301 Users Manual
        DSP56301 Technical Data
        DSP56301 Te chnical Data she et
    - 38Table 2-8. External Bus Control Signals (Continued)
      - Interrupt and Mode Control
- 392.6 Interrupt and Mode Control
  - lock-step
  - Table 2-9. Interrupt and Mode Control
    - 2-10 DSP56301 Users Manual
- 402.7 Host Interface (HI32)
  - Table 2-10 . Host Interface
    - 422-12 DSP56301 Users Manual
    - 2-14 DSP56301 Users Manual
  - 44Table 2-11. Summary of HI32 Signals and Modes
  - Table 2-10 . Host Inter face (Continued)
  - 45Table 2-11. Summary of HI32 Signals and Modes (Continued)
    - 2-16 DSP56301 Users Manual
  - 46Table 2-12 . Host Port Pins (HI32)
  - Table 2-11. Summary of HI32 Signal s and Mode s (Continued)
    - 47n
    - 482-18 DSP56301 Users Manual
    - 49n
    - 502-20 DSP56301 Users Manual
    - 2-22 DSP56301 Users Manual
- 522.8 Enhanced Synchronous Serial Interface 0
  - 53Table 2-13. Enhanced Sy nchronous Serial Interface 0
    - 2-24 DSP56301 Users Manual
  - 54Table 2-13 . Enhanced Synchronous Serial Int erface 0 (Continued)
    - Enhanced Synchronous Serial Interface 1
- 552.9 Enhanced Synchronous Serial Interface 1
  - Table 2-14. Enhanced Serial Synchronous Interface 1
    - Enhanced Synchronous Serial Interface 1
    - 2-26 DSP56301 Users Manual
  - 56Table 2-14 . Enhanced Serial Synchronous Interface 1 (Continued)
    - Serial Communications Interface (SCI)
- 572.10 Serial Communications Interface (SCI)
- 2.11 Timers
  - Table 2-15 . Serial Communication Interface
    - Timers
    - 2-28 DSP56301 Users Manual
  - 58Table 2-16. Triple Timer Signals
    - JTAG and OnCE Interface
- 592.12 JTAG and OnCE Interface
  - Table 2-17 . JTAG/OnCE Interface
61Chapter 3 Memory Configuration
- 3.1 Program Memory Space
  - 623.1.1 Internal Program Memory
  - 3.1.2 Memory Switch ModesProgram Memory
  - 3.1.3 In struction Cache
  - 3.1.4 Program Bootstrap ROM
- 633.2 X Data Memory Space
  - 3.2.1 Internal X Data Memory
  - 3.2.2 Memory Switch ModesX Data Memory
  - 3.2.3 I n ternal I/O SpaceX Data Memory
- 643.3 Y Data Memory Space
  - 3.3.1 Internal Y Data Memory
  - 3.3.2 Memory Switch ModesY Da ta Memory
  - 3.3.3 E xternal I/O SpaceY Data Memory
- 653.4 Dynamic Memory Configuration Switching
  - CAUTION
- 663.5 Sixteen-Bit Compatibility Mode Configuration
- 3.6 Internal Memory Configuration Summary
- 673.7 Memory Maps
  - Figure 3-1. Default Settings (0, 0, 0)
- Default
75Chapter 4 Core Configuration
- 4-2 DSP56301 Users Manual
- 764.1 Operating Modes
  - F1111
  - Table 4-1. DSP56301 Operating Modes
  - 77Table 4-2. Operating Mode Definitions
    - magic number
    - 4-4 DSP56301 Users Manual
  - 78Table 4-2. Operating Mode Definitions (Continued)
    - Bootstrap Program
      - magic number
    - 1. In early revisions of the DSP56301, the size of the bootstrap program is 192 bytes 24 bits.
- 794.2 Bootstrap Program
  - F
  - Table 4-2. Operating Mode Definitions (Continued)
- 804.3 Central Processor Unit (CPU) Registers
  - 4.3.1 S tatus Register (SR)
    - nCondition Code Register (CCR) (SR[70])Defines the results of previous arithmetic
    - 81Figure 4-1. Status Re gister (SR ) Table 4-3. Status Register Bit Definitions
      - 824-8 DSP56301 Users Manual
        83DSP56300 Family Manual
      - 844-10 DSP56301 Users Manual
  - 864.3.2 Operating Mode Register (OMR)
    - Address Attribute Registers (AAR[03])
    - 87Table 4-4. Operating Mode Register (OMR) Bit Definitions (Continued)
      - 884-14 DSP56301 Users Manual
      - n
      - n n n
- 894.4 Configuring Interrupts
  - 4-16 DSP56301 Users Manual
  - 904.4.1 Interrupt Priority Registers (IPRC and IPRP)
    - Figure 4- 3. Interrupt Priority Register-Core (IPRC) (X:$FFFFFF)
    - Figure 4-4. Interrupt Priority Register-Peripherals (IPRP) (X:$FFFFFE)
  - 914.4.2 Interrupt Table Memory Map
    - 4-18 DSP56301 Users Manual
    - 92Table 4-6. Interrupt Sources (Continued)
  - 934.4.3 P roces sing Interrupt Source Priorities Within an IPL
    - Table 4-7. Interrupt Source Priorities Within an IPL
    - Table 4-6. Interrupt Sources (Continued)
      - 4-20 DSP56301 Users Manual
    - 94Table 4-7. Interrupt Source Priorities Within an IPL (Continued)
      - PLL Control Register (PCTL)
- 954.5 PLL Control Register (PCTL)
  - Figure 4-5. PLL Control Register (PCTL) Table 4-8. PLL Control Register (PCTL) Bit Definitions
- 964.6 Bus Interface Unit (BIU) Registers
  - 4.6.1 Bus Control Register
    - 97Table 4-9. Bus Control Register (BCR) Bit Definitions (Continued)
  - 984.6.2 DRAM Control Register (DCR)
    - 99Table 4-10. DRAM Con trol Register (DCR) Bit Defin itions
    - 100Table 4-10. DRAM Control Register (DCR) Bit Definitions (Continued)
  - 1014.6.3 Addre ss Attrib ut e Registers (AAR[03])
    - 4-28 DSP56301 Users Manual
      - Using the DSP56300 Direct Memory Access Controller
    - 102Table 4-11. Address A ttri bute Registers (AAR[03] ) Bit Definiti ons (Conti nued)
- 1034.7 DMA Control Registers 50 (DCR[50])
  - Figure 4-9. DMA Contro l Register (DCR)
    - n n n n
  - Table 4-12. DMA Control Re gister (DCR) Bit Definitions
  - Table 4-11. Address Attribute Registers (AAR[03]) Bit Definitions (Continued)
    - 4-30 DSP56301 Users Manual
  - 104Table 4-12. DMA Control Register (DCR) Bit Definitions (Co ntinued)
    - n
  - 105Table 4-12. DMA Control Register (DCR) Bit Definitions (Continued)
    - 4-32 DSP56301 Users Manual
    - n
  - 106Table 4-12. DMA Control Register (DCR) Bit Definitions (Co ntinued)
  - 107Table 4-12. DMA Control Register (DCR) Bit Definitions (Continued)
    - Device Identification Register (IDR)
      - Inst ruction Cache
    - 4-34 DSP56301 Users Manual
- 1084.8 Device Identification Register (IDR)
  - Figure 4-10. Identification Register Configuration (Revision E)
    - Operating Modes and Memor y Spac es
  - Table 4-12. DM A Control Register (DC R ) Bit Definitions (Contin ued)
- 1094.9 JTAG Identification (ID) Register
- 4.10 JTAG Boundary Scan Register (BSR)
111Chapter 5 Programming the Peripherals
- 5.1 Peripheral Initialization Steps
- 1125.2 Mapping the Control Registers
- 5.3 Data Transfer Methods
  - 5.3.1 Polling
  - 1135.3.2 Interrupts
  - 5.3.3 DMA
  - 5.3.4 Advantages and Disadvantages
- 1145.4 General-Purpose Input/Output (GPIO)
  - General-Purpose Input/Output (GPIO)
    - Programming the Peripherals 5-5
  - 1155.4.1 Port B Signals and Registers
    - (HI32)/
    - (HP)
    - P
    - H
    - Host Interface
    - Port B Signa ls
    - DSP56301
    - As shown in Figure 5-2, you can configure twenty-four Port B signals as GPIO signals.
      - Figure 5-2. Host Interface/Port B Detail Signal Diagram
    - PCI Bus Universal Bus Port B GPIO
    - ost
    - ort
    - Reference
  - 1165.4.2 Port C Signals and Registers
  - 5.4.3 Port D Signals and Registers
  - 5.4.4 Port E Signals and Registers
  - 1175.4.5 Triple Timer Signals and Registers
119Chapter 6 Host Interface (HI32)
- 6.1 Features
  - 120Table 6-1. HI32 Features, Core-Side and Host-Side
  - 121Table 6-2. HI32 Features in PCI Mode and Universal Bus Mode
  - Table 6-1. HI32 Features, Cor e- Side and Host- Si de (Continued)
- 1226.2 Overview
  - Table 6-2. HI32 Features in PCI Mode and Universal Bus Mode (Continued)
  - Figure 6-1. HI32 Block Diagram
  - HOST Bus
  - 123D
  - S
  - P-
  - ide Registers
    - Host-Side Registers
- 1246.3 Data Transfer Paths
  - 6.3.1 Host-to-DSP Data Path
  - 1256.3.2 DSP-To-Host Data Path
    - 126Table 6-3. HI32 (P CI Master Data Transfer Formats
    - 127Table 6-4. Transmit Data Transfer Format
    - Table 6-3. HI32 (P CI Master Data Transfer F ormats (Continue d)
    - 128Table 6-5. Receive Transfer Data Formats
    - Table 6-4. Transmit Data Transfer Format (Continued)
    - 129Table 6-5. Receive Transfer Data Formats
      - Reset States
      - 6-12 DSP56301 Users Manual
- 1306.4 Reset States
  - Table 6-6 describes the various HI32 reset states.
- 6.5 DSP-Side Operating Modes
  - Table 6-6. HI32 Reset
  - 1316.5.1 Termin ate and Reset (DCTR[HM] = $0)
  - 6.5.2 PCI Mode (DCTR[HM] = $1)
    - DSP-Side Operating Modes
    - 6-14 DSP56301 Users Manual
    - 132Example 6-1. PCI /DMA Throughput (32-Bit)
    - Example 6-2. PCI /DMA Throughput (24-Bit)
  - 1336.5.3 Universal (DCTR[HM] = $2) and Enhanced Universal (DCTR[HM] = $3) Bus Modes
  - 1346.5.4 GPIO Mode (DCTR[HM] = $4)
  - 6.5.5 Self-Configuration Mode (DCTR [HM] = $5)
    - DSP-Side Operating Modes
    - 135Example 6-3. Self-Configuration Procedure for PCI Mode
    - Example 6-4. Self-Configuration Procedure for Universal Bus Mode
      - Host Port Pins
      - 6-18 DSP56301 Users Manual
- 1366.6 Host Port Pins
  - Table 6-8. Host Port Pin Functionality
  - 137Figure 6-2. Connection to a PCI Bus
  - DSP56301PCI Bus
  - 138Figure 6-3. Connection to 16-Bit ISA/EISA Data Bus
  - ISA
  - HI32
  - Host
  - 139Figure 6-4. Connection to the DSP56300 Core Port A Bus
  - Port A
- 1406.7 HI32 DSP-Side Programming Model
  - 1416.7.1 DSP Control Register (DCTR)
    - Figure 6-5. DSP Control Register (DCTR) Table 6-10 . DSP Control Register (DCTR) Bit Definitio ns
      - 1426-24 DSP56301 Users Manual
      - 6-26 DSP56301 Users Manual
  - 1446.7.2 DSP PCI Control Register (DPCR)
    - Figure 6-6. DSP PCI Control Register (DPCR)
    - 145Table 6-11 . DSP PCI Control Register (DPCR) Bit Definitions
      - n n
      - n
      - 1466-28 DSP56301 Users Manual
      - n n
      - 6-30 DSP56301 Users Manual
  - 1486.7.3 DSP PCI Master Control Register (DPMC)
    - Figure 6-7. DSP PCI Master Control Reg ister (DPMC)
    - 149Table 6-12 . DSP PCI Master Control Registe r (DMPC) Bit Definitions
      - 6-32 DSP56301 Users Manual
        DSP PCI Address Register (DPAR), on page 6-33
    - 150Table 6-12 . DSP PCI Master Control Register (DMPC) Bit Definitions (Continued)
  - 1516.7.4 DS P PCI Address Register (DPAR)
    - 6-34 DSP56301 Users Manual
    - 152Table 6-13. DSP PCI Address Register (DPAR) Bit Definitions (Continued)
  - 1536.7.5 DS P Status Register (DSR)
    - not
    - HACT
    - Figure 6-9. DSP Status Register (DSR)
    - Table 6-14. DSP Stat us Register (DSR) Bit Definitions
      - n
      - 6-36 DSP56301 Users Manual
      - n n
    - 154Table 6-14. DSP Status Register (DSR) Bi t Definitions (Continued)
      - n
    - 155Table 6-14. DSP Status Register (DSR) Bit Definitions (Continued)
      - 6-38 DSP56301 Users Manual
  - 1566.7.6 DS P PCI Status Register (DPSR)
    - n
    - 157Table 6-15. DSP PCI Status Register (DPSR) Bit Definitions (Continued)
      - 1586-40 DSP56301 Users Manual
      - n
  - 1596.7.7 DSP Receive Data FIFO (DRXR)
  - 1606.7.8 DSP Maste r Tran sm it Data Re gister ( D TX M )
  - 6.7.9 DSP Slave Transmit Data Register (DTXS)
  - 1616.7.10 DSP Host Port GPIO Direction Register (DIRH)
  - 6.7.11 DSP Host Port GPIO Data Register (DATH)
- 1626.8 Host-Side Programming Model
  - The HI32 appears to the host processor as a bank of registers, listed in Table 6-17.
  - In the Universal Bus modes:
  - Table 6-17. HI32 Programming Model, Host-Side Registers
    - 6-46 DSP56301 Users Manual
    - nThe HI32 does not reach deadlock due to illegal PCI events. Illegal PCI events bring
  - 164the HI32 master and target state machines to the idle state.
    - Table 6-18. PCI Bus Co mmands
  - 165
    - Host Transmit/Slave Receive Data Register (HTXR/HRXS) (16377 Dwords)
    - Table 6-20. Host-Side Registers (PCI Configuration Address Space1)
    - Table 6-21. Host-Side Registers (Universal Bus Mode Address Space1)
  - 1666.8.1 HI32 Control Register (HCTR)
    - 167Table 6-22. Host Interface Cont rol Register (HCTR) Bit Definitions
      - n
      - 1686-50 DSP56301 Users Manual
        Receive Transfer Data Formats
      - n
        Transmit Data Transfer Format
      - 169n
      - n n
      - n
      - 1706-52 DSP56301 Users Manual
      - n n
      - 1726-54 DSP56301 Users Manual
      - n n
      - 6-56 DSP56301 Users Manual
  - 1746.8.2 Host Interface Status Register (HSTR)
    - Figure 6-14. Host Interface Status Register (HSTR)
    - nWhen the HSTR is read to the PCI bus (DCTR[HM] = $1), the HAD[31 0] pins are
    - driven with the HSTR data during a read access.
      - nIn a 24-bit data Universal Bus mode (DCTR[HM] = $2 or $3 and HCTR[HRF] = $0),
    - the HD[230] pins are driven with the three least significant HSTR bytes during a read access.
      - Table 6-22. Host Interface Control Register (HCTR) Bit Definitions (Continued)
        6-58 DSP56301 Users Manual
      - 176Table 6-23 . Host Interface Status Regist er (HST R) Bit Definitions (Continued)
  - 1776.8.3 Host Command Vector Register (HCVR)
    - 6-60 DSP56301 Users Manual
    - 178Table 6-24. Host Command Vector Register (H CVR) Bit Definitions
  - 1796.8.4 Host Master Receive Data Register (HRXM)
  - 6.8.5 Host Sl ave Receive Data Register (HRXS)
  - 1806.8.6 Host Tra nsmit Data Register (HTXR)
  - 1826.8.7 Device ID/Vendor ID Configuration Register (CDID/CVID)
  - 6.8.8 Status/Command Configuration Register (CSTR/CCMR)
    - 183Table 6-26. Status/Command Configuration Register (CSTR/CCMR) Bit Definitions
      - 6-66 DSP56301 Users Manual
      - Wait Cycle Control (hardwired to zero)
      - Bus Master Enable
    - 184Table 6-26. Status/Command Configuration Register (CSTR/CCMR) Bit Definitions
  - 1856.8.9 Class Code/Revision ID Configuration Register (CCCR/CRID)
    - Figure 6-18. Class Code/Revision ID Configuration Register CCCR/CRID)
    - Table 6-27. Class Code/Revision ID Configurat ion Register (CCCR/CRID) Bit Definitions
  - 1866.8.10 Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS)
    - 6-70 DSP56301 Users Manual
  - 1886.8.11 Memory Space Base Address Configuration Register (CBMA)
    - Figure 6-20. Memory Space Base Address Configuration Register (CBMA)
    - Table 6-29. Memory Space Base Address Configuration Register (CBMA) Bit Definitions
  - 1896.8.12 Subsystem ID and Subsystem Vendor ID Configuration Register (CSID)
  - 1916.8.13 Interrupt Line-Interrupt Pin Configuration Register(CILP)
    - Figure 6-22. Interrupt Line-Interrupt Pin Configurat ion Register(CILP)
    - Table 6-30 . Interrupt Line-Interrupt Pin Configuration Register(CILP) Bit Definitions
      - 6-74 DSP56301 Users Manual
- 1926.9 HI32 Programming Model/Quick Reference
  - 1946-76 DSP56301 Users Manual
  - 1966-78 DSP56301 Users Manual
  - 1986-80 DSP56301 Users Manual
  - 1. STRQ. MTRQ are zero in the personal software reset state.
199Chapter 7 Enhanced Synchronous Serial Interface (ESSI)
- Figure 7-1. ESSI Block Diagram
- 2007.1 ESSI Enhancements
- 2017.2 ESSI Data and Control Signals
  - 7.2.1 S erial Transmit Data Signal (STD)
  - 7.2.2 Serial Receive Data Signal (SRD)
  - 7.2.3 Serial Clock (SCK)
  - 2027.2.4 Serial Control Signal (SC0)
  - 7.2.5 Serial Control Signal (SC1)
    - ESSI Data and Control Signals
    - 203Table 7-2. Mode and Signal Definitions
  - 7.2.6 Serial Control Signal (SC2)
- 2047.3 Operation
  - 7.3.1 ESSI After Reset
  - 7.3.2 Initialization
  - 2057.3.3 Exceptions
- 2087.4 Operating Modes: Normal, Network, and On-Demand
  - 7.4.1 Normal/Network/On-Demand Mode Selection
  - 2097.4.2 Synchronous/Asynchronou s O perating Mod es
  - 7.4.3 Frame Sync Selection
  - 7.4.4 Frame Sync Signal Format
  - 2107.4.5 Frame Sync Length for Multiple Devices
  - 7.4.6 Word Length Frame Sync and Data Word Timing
  - 7.4.7 Fr ame Sync Polarity
  - 2117.4.8 Byte Format (LSB/MSB) for the Transmitter
  - 7.4.9 Flags
- 2127.5 ESSI Programming Model
  - 7.5.1 ESSI Control Register A (CRA)
    - 213Table 7-3. ESSI Control Register A (CRA) Bit Definitions
      - n n
      - 7-16 DSP56301 Users Manual
    - 214Table 7-3. ESSI Control Register A (CRA) Bit Definitions (Continued)
    - 215Figure 7-3. ESSI Clock Generator Functional Block Diagram
    - Figure 7-4. ESSI Frame Sync Generator Functional Block Diagram
  - 2167.5.2 ESSI Control Register B (CRB)
    - 217Table 7-4. ESSI Control Register B (CRB) Bit Definitions
      - 2187-20 DSP56301 Users Manual
      - 2207-22 DSP56301 Users Manual
    - 222Figure 7-6. CRB FSL0 and FSL1 Bit Operation (FSR = 0)
      - 7-24 DSP56301 Users Manual
    - 223Figure 7-7. CRB SYN Bit Operation
      - Enhanced Synchronous Serial Interface (ESSI) 7-25
      - ESSI Bit Clock
      - Note: Transmitter and receiver may have the same clock frame syncs.
      - Note: Transmitter and receiver may have different clocks and frame syncs.
      - ESSI Bit Clock
      - 7-26 DSP56301 Users Manual
    - 224Figure 7-8. CRB MOD Bit Operation
    - 225Figure 7-9. Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame)
    - Figure 7-10. Network Mode, External Frame Sync (8 Bit, 2 Words in Frame)
      - 7-28 DSP56301 Users Manual
  - 2267.5.3 ESSI Status Regi ster (SSISR)
    - Figure 7-11. ESSI Status Re giste r (S SIS R)
    - Table 7-5. ESSI Status Register (SSISR) Bit Definitions
  - 2277.5.4 ESSI Receive Shift Register
    - Table 7-5. ESSI Status Register (SSISR) Bit Definitions (Continued)
  - 2287.5.5 ESSI Receive Data Register (RX)
  - 7.5.6 ESSI Transmit Shift Registers
    - 229Figure 7-12. ESSI Data Path Programming Model (SHFD = 0)
    - 230Figure 7-13. ESSI Data Path Programming Model (SHFD = 1)
      - 7-32 DSP56301 Users Manual
  - 2317.5.7 ESSI Transmit Data Registers (TX[20])
  - 7.5.8 E SSI Time Slot Register (TSR)
  - 7.5.9 Transmit Slot Mask Registers (TSMA, TSMB)
  - 2337.5.10 Receive Slot Mask Registers (RSMA, RSMB)
- 2347.6 GPIO Signals and Registers
  - 7.6.1 Port Control Registers (PCRC and PCRD)
  - 2357.6.2 Port Direction Registers (PRRC and PRRD)
  - 2367.6.3 Port Data Registers (PDRC and PDRD)
237Chapter 8 Serial Communication Interface (SCI)
- 8.1 Operating Modes
  - 2388.1.1 Synchronous Mode
  - 8.1.2 Asynchronous Mode
  - 8.1.3 Multidrop Mode
- 2398.2 I/O Signals
  - 2408.2.1 Receive Data (RXD)
  - 8.2.2 Transmit Data (TXD)
  - 8.2.3 S C I Serial Clock (SCLK)
- 2418.3 SCI After Reset
  - SCI Initialization
  - 8-6 DSP56301 Users Manual
- 2428.4 SCI Initialization
  - Table 8-1. SCI Registers After Reset (Continued)
  - 2438.4.1 Preamble, Break, and Data Transmission Priority
  - 8.4.2 Bootstrap Loading Through the SCI (Boot Mode 2 or A)
- 2448.5 Exceptions
- 2458.6 SCI Programming Model
  - 246Figure 8-1. SCI Data Word Formats (SSFTD = 1), 1
    - 8-10 DSP56301 Users Manual
  - 247Figure 8-2. SCI Data Word Formats (SSFTD = 0), 2
    - 8-12 DSP56301 Users Manual
  - 2488.6.1 SCI Control Register (SCR)
    - Figure 8-3. SCI Control Register (SCR) Table 8-2. SCI Control Register (SCR) Bit Definitions
  - 2538.6.2 S C I Status Register (SSR)
    - The SSR is a read-only register that indicates the status of the SCI.
      - Table 8-3. SCI Status Register Table 8-4. SCI Status Register (SSR) Bit Definitions
        8-18 DSP56301 Users Manual
      - 254Table 8-4. SCI Status Register (SSR) Bit Definitions (Continued)
  - 2558.6.3 SCI Clock Control Register (SCCR)
    - RESET signal.
    - n
    - 8-20 DSP56301 Users Manual
    - 256Figure 8-5. SCI Baud Rate Generator
    - Table 8-5. SCI Clock Control Re gister (SCCR) Bit Definitions (Continued)
  - 2588.6.4 SCI Data Registers
- 2608.7 GPIO Signals and Registers
  - 8.7.1 Port E Control Register (PCRE)
  - 2618.7.2 P ort E Direction Register (PRRE)
  - 8.7.3 Por t E Data Re gister (P DRE)
263Chapter 9 Triple Timer Module
- 9.1 Overview
  - 2649.1.1 Triple Timer Module Block Diagram
  - 9.1.2 I ndividual Timer Block Diagram
- 2659.2 Operation
  - 9.2.1 Ti mer Af ter Reset
  - 2669.2.2 Ti mer Initialization
  - 9.2.3 Timer Exceptions
- 2679.3 Operating Modes
  - 2689.3.1 Triple Timer Modes
    - 269Figure 9-3. Timer Mode (TRM = 1)
    - Figure 9-4. Timer Mode (TRM = 0)
    - 271Figure 9-6. Pulse Mode (TRM = 0)
    - 273Figure 9-8. Toggle Mode, TRM = 0
      - Mode 2 (internal clock): TRM = 0
    - 275Figure 9-10. Event Counter Mode, TRM = 0
  - 2769.3.2 Signal Measurement Modes
    - 277Figure 9-11. Pulse Width Measurement Mode, TRM = 1
    - Figure 9-12. Pulse Width Measurement Mode, TRM = 0
    - 279Figure 9-14. Period Measurement Mode, TRM = 0
  - 2819.3.3 Pulse Width Modulation (PWM, Mode 7)
    - 282Figure 9-16. Pulse Width Modulation Toggle Mode, TRM = 1
      - M
      - M + 1
    - 283Figure 9-17. Pulse Width Modulation Toggle Mode, TRM = 0
      - M
      - M + 1
  - 2849.3.4 Watchdog Modes
    - 285Figure 9-18. Watchdog Pulse Mode
      - Mode 9 (internal clock): TRM = 0
        M
        M + 1
  - 9.3.5 Special Cases
  - 9.3.6 DMA Trigger
- 2879.4 Triple Timer Module Programming Model
  - 9.4.1 P rescaler Counter
    - 288Figure 9-20. Timer Modul e Programmers Model
  - 2899.4.2 Timer Prescaler Load Register (TPLR)
    - 9-28 DSP56301 Users Manual
  - 2909.4.3 Timer Prescaler Count Register (TPCR)
    - The TPCR is a read-only register that reflects the current value in the prescaler counter.
    - The TCSR is a read/write register controlling the timer and reflecting its status.
  - 9.4.4 Timer Control/Status Register (TCSR)
    - 2929-30 DSP56301 Users Manual
      - 293Operati ng Mode s
    - 9-32 DSP56301 Users Manual
    - 294Table 9-4. Inverter (INV) Bit Operation
  - 2959.4.5 Timer Load Register (TLR)
  - 2969.4.6 Timer Compare Register (TCPR)
  - 9.4.7 Timer Count Register (TCR)
    - DSP56301 Users Manual A-1
297Appendix A Bootstrap Program
- This appendix lists the bootstrap program for the DSP56301.
313Chapter B Programming Reference
- B-2 DSP56301 Users Manual
- 314Table B-1. Guide to Programming Sheets
- 315B.1 Internal I/O Memory Map
  - Table B-2. Internal I/O Memory Map (X Data Memory)
- 321B.2 Interrupt Sources and Priorities
  - Table B-3. Interrup t Sources
    - B-10 DSP56301 Users Manual
  - 322Table B-3. Interrupt Sources (Continued)
  - 323Tab le B -4. Interrupt Source Priorities Within an IPL
    - B-12 DSP56301 Users Manual
  - 324Table B-4. Interrupt Source Priorities Within an IPL (Continued)
- B.3 Programming Sheets
  - Figure B-1. Status Register (SR)
325Central Processor
- Figure B-2. Operating Mode Register (OMR)
  - B-14 DSP56301 Users Manual
    - Chip Operating Modes
      - 0 = no 1 = underflow
      - 0 = no 1 = overflow
      - 0 = no wrap 1 = wrap (sticky bit)
  - Bus Release Timing
  - Asynchronous Bus Arbitration Enable
  - Address Attribute Priority Disable
  - 19 18 17 1 6 23 22 21 20
    - Sheet 2 of 2
    - Core-DMA Priority
      - Chip Operating Mode Register (COM)
      - System Stack Control Status Registe r (SCS) Extended Chip Operating
      - Mode Register (EOM)
  - Operati ng Mode Register (OMR ) Read/Write Reset = $00030X; X = latched from levels on Mode pins
326Central Processor
- Burst Mode Enable TA Synchronize Select
- Memory Switch Mode
- External Bus Disable Stop Delay
  - 0 = enable 1 = disable 0 = 128 K clocks 1 = 16 clocks
  - 0 = not selected 1 = selected 0 = fast 1 = slow
  - 0 = enable 1 = disable
  - 0 = X memor y 1 = Y memory
- Stack Extension Enable
- Figure B-3. Interrupt Priority Register Core (IPRC)
  - Programming Reference B-15
    - Sheet 1 of 2
327 Interrupt Priority
- IRQA Mode
- IRQB Mode
- IRQC Mode
- IRQD Mode
- Interrupt Priority Register (IPRC) X:$FFFFFF Read/Write
  - DMA5 IPL
    - DMA4 IPL
  - DMA3 IPL
  - DMA2 IPL
  - DMA1 IPL
  - DMA0 IPL
- Figure B-5. Phase-Locked Loop Control Register (PCTL)
  - Programming Reference B-17
    - Sheet 1 of 1
329PLL
- 19 18 17 16 23 22 21 20 PLL Control Register (PCTL) X:$FFFFFD Read/Write
  - XTAL Disable Bit (XTLD) 0 = Enable Xtal Oscillator 1 = EXTAL Driven From An External Source
  - Clock Output Disable (COD) 0 = 50% Duty Cycle Clock 1 = Pin Held In High State
  - Crystal Range Bit (XTLR) 0 = External Xtal Freq > 200KHz 1 = External Xtal Freq < 200KHz
- 330Figure B-6. Bus Control Register (BCR)
- 331Figure B-7. DRAM Con tr ol Re gister (DCR)
  - X:$FFFFFA Read/Write
    - Programming Reference B-19
  - DRAM Control Register (DCR)
- 332Figure B-8. Address Attribute Registers (AAR[30])
  - B-20 DSP56301 Users Manual
  - Address Attribute Registers 3 (AAR3)
333DMA
- Figure B-9. DMA Cont rol Registers 50 (D CR[50])
  - Programming Reference B-21
  - DMA Control Registers (DCR5DCR0)
  - X:$FFFFD8, X:$FFFFDC, X:$F FFFE0,
  - X:$FFFFE4, X:$FFFFE8, X:$FFFFEC Read/Write
    - Non-Three-Dimensional Addressing Modes (D3D=0)
    - Three-Dimensional Addressing Modes (D3D=1)
  - Progra mmer:
- 3340
  - Read/Write Address: X: FFFFC5
  - Figure B-10. DSP Control Register (DCTR)
    - B-22 DSP56301 Users Manual
    - DSP Control Register (DCTR)
- 3350TCIE TTIE *
- 0TAIE *
  - Address: X:FFFFC6 Read/Write
  - Note: All bits work only in PCI mode (DCTR[HM] = $1).
  - Figure B-11. DSP PCI Control Reg ister (DPCR)
    - Programming Reference B-23
    - DSP PCI Control Register (DPCR)
  - 336Figure B-12. DSP PCI Master Control Reg ister (DPMC)
  - 337Figure B-13. DSP PCI Address Registe r (DPAR)
    - Programming Reference B-25
    - DSP PCI Address Register (DPAR)
    - Note: All bits work only in PCI mode (DCTR[HM] = $1). You can write to the DPAR only if MARQ is set.
    - 19 18 17 1 6 23 22 21 20
    - Address: X:FFFFC7 Read/Write
      - PCI Byte Enables, Bits 2320
      - BE[30] enable byte lanes 30, respectively.
        Sheet 4 of 10
      - PCI Bus Command, Bits 1916
      - Defines PCI bus commands, as follows:
        DSP PCI Transaction Address (Low)
  - 338Figure B-14. HI32 Control Register (HCTR)
    - UB Host-to-DSP (DCTR[HM] = $2 or $3)
    - DSP-to-UB Host (DCTR[HM] = $2 or $3)
    - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 019 18 17 1623 22 21 20
    - Read/Write
    - B-26 DSP56301 Users Manual
    - HI32 Control Register (HCTR) Reset = $00000000
    - 27 26 25 2431 30 29 28
      - DSP-to-PCI Host (DCTR[HM] = $1)
      - PCI Host-to-DSP (DCTR[HM] = $1)
  - 342Figure B-18. Memory Space Base Address Configuration Register (CBMA)
  - 343Figure B-19. Subsystem ID and Subsystem Vendor ID Configuration Register (CSID)
  - Figure B-20. ESSI Co nt r o l Re gi s ter A (CRA)
    - B-32 DSP56301 Users Manual
      - Sheet 1 of 3
- 3440
  - 19 18 17 16 23 22 21 20
  - ESSI Control Register A (CRAx) ESSI0X:$FFFFB5 Read/Write ESSI1X:$FFFFA5 Read/WriteReset = $000000
  - 345Figure B-21. ESSI Co nt r o l Re gi s ter B (CRB)
    - Programming Reference B-33
- 3460
  - Figure B-22. ESSI Transmit and Receive Slot Mask Registers (TSM, RSM)
- 0
  - Figure B-23. SCI Control Register (SCR)
    - Programming Reference B-35
347SCI
- Reset $000000
- 16
- X:$FFFF9C Read/Write
- SCI Control Register (SCR)
- *
  - 23
  - 0
    - Figure B-24. SCI Clock Control Registers (SCCR)
348SCI
- 0
  - Figure B-25. Timer Prescaler Load Register (TPLR)
- 3490
  - 350Figure B-26. Time r C ontrol/ Sta t us Re gi s ter (TCS R)
    - B-38 DSP56301 Users Manual
  - 351Figure B-27. Timer Loa d Regi ste rs (TL R)
  - Figure B-28. Host Data Direction and Host Data Registers (HDDR, HDR)
352GPIO
- Figure B-29. Port C Register s (PCRC, PRRC, PDRC)
353GPIO
- Figure B-30. Port D Register s (PCRD, PRRD, PDRD)
354GPIO
357Index
- A
- B
- 358C
- D
- 360E
- 361F
- 362G
  - ,
- H
- 365I
- J
- L
- M
- 366N
- O
- P
- 367R
- 368S
  - 369,
- 370T
- 371U
- V
- W
- X
- 372Y
- Z