Omron FQM1-MMA21, FQM1-CM001, FQM1-MMP21 Data Shift Instructions, Increment/Decrement Instructions

Auxiliary Area Allocations						Appendix D
Data Shift Instructions
Instruction	Mnemonic	Code	Length	ON execution	Hardware	Conditions
			(steps)	time (∝s)	implementation
			(See
			note.)
SHIFT REGISTER	SFT	010	3	12.4	---	Shifting 1 word
				368.1	---	Shifting 1,000 words
REVERSIBLE SHIFT	SFTR	084	4	14.0	---	Shifting 1 word
REGISTER
				1.44 ms	---	Shifting 1,000 words
ASYNCHRONOUS	ASFT	017	4	13.9	---	Shifting 1 word
SHIFT REGISTER
				3.915 ms	---	Shifting 1,000 words
WORD SHIFT	WSFT	016	4	9.7	---	Shifting 1 word
				728.1	---	Shifting 1,000 words
ARITHMETIC SHIFT	ASL	025	2	0.45	Yes	---
LEFT
DOUBLE SHIFT LEFT	ASLL	570	2	0.80	Yes	---
ARITHMETIC SHIFT	ASR	026	2	0.45	Yes	---
RIGHT
DOUBLE SHIFT	ASRL	571	2	0.80	Yes	---
RIGHT
ROTATE LEFT	ROL	027	2	0.45	Yes	---
DOUBLE ROTATE	ROLL	572	2	0.80	Yes	---
LEFT
ROTATE LEFT WITH-	RLNC	574	2	0.45	Yes	---
OUT CARRY
DOUBLE ROTATE	RLNL	576	2	0.80	Yes	---
LEFT WITHOUT
CARRY
ROTATE RIGHT	ROR	028	2	0.45	Yes	---
DOUBLE ROTATE	RORL	573	2	0.80	Yes	---
RIGHT
ROTATE RIGHT WITH-	RRNC	575	2	0.45	Yes	---
OUT CARRY
DOUBLE ROTATE	RRNL	577	2	0.80	Yes	---
RIGHT WITHOUT
CARRY
ONE DIGIT SHIFT	SLD	074	3	10.1	---	Shifting 1 word
LEFT
				1.208 ms	---	Shifting 1,000 words
ONE DIGIT SHIFT	SRD	075	3	11.7	---	Shifting 1 word
RIGHT
				1.775 ms	---	Shifting 1,000 words

Note When a double-length operand is used, add 1 to the value shown in the length column in the above table.

Increment/Decrement Instructions

Instruction	Mnemonic	Code	Length	ON execution	Hardware	Conditions
			(steps)	time (∝s)	implementation
			(See
			note.)
INCREMENT BINARY	++	590	2	0.45	Yes	---
DOUBLE INCRE-	++L	591	2	0.80	Yes	---
MENT BINARY
DECREMENT BINARY	– –	592	2	0.45	Yes	---
DOUBLE DECRE-	– –L	593	2	0.80	Yes	---
MENT BINARY
INCREMENT BCD	++B	594	2	12.1	---	---
DOUBLE INCRE-	++BL	595	2	9.37	---	---
MENT BCD
DECREMENT BCD	– –B	596	2	11.5	---	---
DOUBLE DECRE-	– –BL	597	2	9.3	---	---
MENT BCD

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