Omron FQM1-CM001, FQM1-MMA21 Pulse Inputs, Section, Example Latching High-speed Counter PV

Pulse Inputs Section 7-5

Example 3:

Latching High-speed

Counter PV

In this example, pulse input 1 operates a high-speed counter, the high-speed counter PV is latched, and the captured high-speed counter PV is read. When the Latch Input 1 Enable Bit is ON and the latch input 1 is turned OFF→ON externally, the high-speed counter PV is captured to the latch register and the Count Latched Flag is turned ON during the next I/O refreshing.

The Count Latched Flag is used as a trigger for the PRV(881) instruction to read the captured high-speed counter PV and the Count Latched Flag is then turned OFF.

If latch input 1 is turned ON again while the Count Latched Flag is still ON (before the captured PV has been read by the PRV(881) instruction), the old captured PV will be refreshed with the new captured PV.

ON

Latch Input 1

Enable Bit

OFF

ON

Latch input 1

OFF

ON

Count Latched

Flag

OFF

PRV instruction execution

High-speed

Counter PV

0

Latch register value 1

Clear Latch

PRV instruction execution

PRV

#0001 Dummy read of

#0002 latch register W000

Start Latch
Latch Input 1	Count Latched
Enable Bit	Flag

A610.08

PRV

Latch Input 1 Enable Bit

A610.08 A608.08

#0001 Read latched high-speed

#0002 counter PV. D00000

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